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公开(公告)号：US12027218B2
公开(公告)日：2024-07-02
申请号：US17554321
申请日：2021-12-17
发明人： Xue Bai Pitner , Prafful Golani , Ravi Kumar
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/26 , H10B41/27 , H10B43/27
摘要： A method for performing a program verify operation with respect to a target memory cell in a memory structure of a non-volatile memory system is provided. The method may include the step of determining a location of the target memory cell within the structure and, based upon the determined location of the target cell and with respect to each programmable memory state: (1) applying a first sense signal at a first point in time, and (2) applying a second sense signal at a second point in time. A time interval between the first and the second points in time is equal to a predetermined optimal time period plus or minus an offset parameter time value.
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公开(公告)号：US12027214B2
公开(公告)日：2024-07-02
申请号：US17949255
申请日：2022-09-21
发明人： Che-Wei Chang
摘要： A sensing device for a non-volatile memory includes a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first terminal of the first switch is connected with the first node and a control terminal of the first switch receives an inverted reset pulse. A first terminal of the second switch is connected with the first node, a second terminal of the second switch receives a ground voltage, and a control terminal of the second switch receives a reset pulse. The sensing circuit is connected between the second terminal of the first switch and a second node. The sensing circuit generates a first sensed current. The judging circuit is connected to the second node. The judging circuit receives the first sensed current and generates an output data according to the first sensed current.
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公开(公告)号：US12027211B2
公开(公告)日：2024-07-02
申请号：US17825439
申请日：2022-05-26
发明人： Zhongguang Xu , Tingjun Xie , Murong Lang
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3404
摘要： A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.
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公开(公告)号：US12020756B2
公开(公告)日：2024-06-25
申请号：US18134719
申请日：2023-04-14
申请人： Kioxia Corporation
发明人： Noboru Shibata , Hironori Uchikawa , Taira Shibuya
IPC分类号： G11C16/00 , G06F3/06 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/34 , H10B69/00
CPC分类号： G11C16/26 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/32 , G11C16/3459 , H10B69/00
摘要： A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.
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公开(公告)号：US20240206171A1
公开(公告)日：2024-06-20
申请号：US18352025
申请日：2023-07-13
发明人： Masaaki HIGASHITANI , Peter RABKIN , Hiroyuki KINOSHITA , Satoshi SHIMIZU , Yanli ZHANG , Johann ALSMEIER
摘要： A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.
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公开(公告)号：US20240206169A1
公开(公告)日：2024-06-20
申请号：US18351992
申请日：2023-07-13
摘要： A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.
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公开(公告)号：US12014782B2
公开(公告)日：2024-06-18
申请号：US17561228
申请日：2021-12-23
申请人： SK hynix Inc.
发明人： Jung Hyeong Kim
摘要： A memory device includes a memory block to which a plurality of lines are connected. The memory device also includes a plurality of memory cells respectively connected to word lines among the plurality of lines, wherein the plurality of memory cells are formed as a plurality of plug holes formed in a stack structure between a drain select line among the plurality of lines and a slit. The memory device further includes a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines among the plurality of lines. The memory device additionally includes a peripheral circuit for performing a read operation on the plurality of memory cells. The peripheral circuit includes a voltage generator configured to control a signal applied to the plurality of page buffers so that the read operation is performed according to positions of the plug holes.
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公开(公告)号：US12014781B2
公开(公告)日：2024-06-18
申请号：US17507326
申请日：2021-10-21
申请人： SK hynix Inc.
发明人： Won Jae Choi , Jea Won Choi
CPC分类号： G11C16/14 , G11C7/1039 , G11C16/26 , G11C16/30
摘要： A memory system includes a first memory die including multiple planes each including a plurality of memory cells and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die. After transferring an erase command to a plane among the multiple planes, the controller transfers a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane.
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公开(公告)号：US20240194277A1
公开(公告)日：2024-06-13
申请号：US18360306
申请日：2023-07-27
发明人： Jiacen Guo , Xiang Yang , Yi Song , Jiahui Yuan
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/26
摘要： Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.
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公开(公告)号：US12008268B2
公开(公告)日：2024-06-11
申请号：US17867008
申请日：2022-07-18
发明人： Daehoon Na , Jeongdon Ihm , Jangwoo Lee , Byunghoon Jeong
CPC分类号： G06F3/0659 , G06F1/06 , G06F3/0611 , G06F3/0656 , G06F3/0679 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/0483
摘要： A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
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