公开(公告)号：US20170344421A1

公开(公告)日：2017-11-30

申请号：US15168045

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0411

Abstract: A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ECC) bits. The first error counter counts errors in the returned data, and provides a control signal in response to reaching a predetermined state. The scrubber controls the memory channel controller to read data sequentially and periodically from a plurality of addresses of a memory system, and in response to detecting a correctable error, to rewrite corrected data. The data processor is responsive to the control signal to perform a post package repair operation with the memory system in response to the control signal.

公开(公告)号：US09825843B2

公开(公告)日：2017-11-21

申请号：US14715023

申请日：2015-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: H01L25/065 ,  H01L23/498 ,  H04L12/755 ,  G06F17/50 ,  H01L23/48 ,  H01L23/538 ,  H04L12/701 ,  H01L25/18

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

公开(公告)号：US09806908B2

公开(公告)日：2017-10-31

申请号：US14620342

申请日：2015-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael E. James

IPC: H04L12/28 ,  H04L12/64

CPC classification number: H04L12/6418

Abstract: Each compute node of a cluster compute server generates and maintains route information for routing messages to other nodes of the server. Each compute node identifies the other nodes connected to a fabric interconnect and generates, based on a set of routing constraints, routes to each of the other nodes. Each compute node communicates messages to other nodes of the server via the generated routes. Because the routes are generated at each compute node the processing load to generate the routes is distributed among the compute nodes.

公开(公告)号：US09799954B2

公开(公告)日：2017-10-24

申请号：US14472824

申请日：2014-08-29

Applicant: Nitero Pty Ltd.

Inventor： Stevan Preradovic ,  Natalino Camilleri ,  Pat Kelly

IPC: H04M1/00 ,  H01Q3/24 ,  H01Q21/20 ,  H01Q23/00

CPC classification number: H01Q3/24 ,  H01Q21/205 ,  H01Q23/00

Abstract: An apparatus for reducing interference and improving communication quality for RF communications over mm-wave frequency bands between wireless communications devices. In one embodiment, for example, the apparatus comprises a plurality of high-gain directional antenna elements each configured to maximally radiate in different directions relative to the apparatus. The apparatus also includes a RFIC chip electrically coupled to the plurality of antenna elements and configured to switch from driving any one of the directional antenna elements to driving another of the directional antenna elements thereby providing a multi-directional or near omni-directional radiation capability for a wireless communications device.

公开(公告)号：US09793919B1

公开(公告)日：2017-10-17

申请号：US15373105

申请日：2016-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard

IPC: H03M7/00 ,  H03M7/30 ,  H04B1/40 ,  H04L27/26 ,  H04L1/06 ,  H04L1/00 ,  H04L25/02

CPC classification number: H03M7/30 ,  G06K9/6202 ,  H03M7/3084 ,  H03M7/42 ,  H04B1/40 ,  H04L1/0003 ,  H04L1/0618 ,  H04L25/0266 ,  H04L27/2647 ,  H04L67/14

Abstract: Systems, apparatuses, and methods for compression of frequent data values across narrow links are disclosed. In one embodiment, a system includes a processor, a link interface unit, and a communication link. The link interface unit is configured to receive a data stream for transmission over the communication link, wherein the data stream is generated by the processor. The link interface unit determines if blocks of data of a first size from the data stream match one or more first data patterns and the link interface unit determines if blocks of data of a second size from the data stream match one or more second data patterns. The link interface unit sends, over the communication link, only blocks of data which do not match the first or second data patterns.

公开(公告)号：US09785345B2

公开(公告)日：2017-10-10

申请号：US15379956

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Yunpeng Zhu ,  Xianshuai Shi ,  Yan Liu

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0604 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/401 ,  G06F2212/657 ,  Y02D10/13

Abstract: A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. When the first functional module is in the first mode, access to the embedded memory element is limited to the first functional module. At least one of the one or more other functional modules is provided with access to the embedded memory element based at least in part on the first functional module being in the second mode.

公开(公告)号：US09785218B2

公开(公告)日：2017-10-10

申请号：US14846058

申请日：2015-09-04

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Adam N. C. Clark ,  Ashish Jain ,  Sridhar V. Gada

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

公开(公告)号：US09778934B2

公开(公告)日：2017-10-03

申请号：US12947401

申请日：2010-11-16

Applicant: Anthony Jarvis ,  James David Dundas

Inventor： Anthony Jarvis ,  James David Dundas

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3804

Abstract: A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed.

公开(公告)号：US20170277441A1

公开(公告)日：2017-09-28

申请号：US15331270

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Gupta ,  David A. Roberts ,  Mitesh R. Meswani ,  Vilas Sridharan ,  Steven Raasch ,  Daniel I. Lowell

IPC: G06F3/06

CPC classification number: G06F12/02

Abstract: Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.

公开(公告)号：US09767043B2

公开(公告)日：2017-09-19

申请号：US14229420

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/126 ,  G06F3/06 ,  G06F12/00 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/126 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0628 ,  G06F3/0653 ,  G06F3/0673 ,  G06F3/0674 ,  G06F3/0676 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0871 ,  G06F12/12 ,  G06F12/121

Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.