公开(公告)号：US11680870B2

公开(公告)日：2023-06-20

申请号：US17516165

申请日：2021-11-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Grosse ,  Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01M11/02 ,  G02B6/28 ,  G02B6/34 ,  G02B6/12 ,  G02B6/00 ,  G01M11/00 ,  G01R31/265 ,  G01R31/27 ,  G01R31/28 ,  G01R31/303 ,  G01R31/311 ,  G01R31/317 ,  G01R35/00

CPC classification number: G01M11/02 ,  G01M11/33 ,  G01R31/2656 ,  G01R31/27 ,  G01R31/2884 ,  G01R31/303 ,  G01R31/311 ,  G01R31/31728 ,  G01R35/00 ,  G02B6/00 ,  G02B6/12004 ,  G02B6/2808 ,  G02B6/34

Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

公开(公告)号：US11677024B2

公开(公告)日：2023-06-13

申请号：US17323545

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean ,  Julien Ferrand

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/07 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/0705 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.

公开(公告)号：US11676985B2

公开(公告)日：2023-06-13

申请号：US17122394

申请日：2020-12-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14603 ,  H01L27/14616

Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.

公开(公告)号：US20230164459A1

公开(公告)日：2023-05-25

申请号：US17986505

申请日：2022-11-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY ,  Thomas DALLEAU

IPC: H04N5/3745 ,  H04N5/378

CPC classification number: H04N5/3745 ,  H04N5/378

Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.

公开(公告)号：US20230163057A1

公开(公告)日：2023-05-25

申请号：US18095629

申请日：2023-01-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Pierre CARRERE ,  Francois GUYADER

IPC: H01L23/498 ,  H01L21/48 ,  H01L31/02

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49894 ,  H01L31/02016

Abstract: A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

公开(公告)号：US11653577B2

公开(公告)日：2023-05-16

申请号：US17112842

申请日：2020-12-04

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique Et Aux Energies Alternatives

Inventor： Jean-Philippe Reynard ,  Sylvie Del Medico ,  Philippe Brun

IPC: H01L45/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L27/222 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L45/06 ,  H01L45/1233

Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.

公开(公告)号：US11621324B2

公开(公告)日：2023-04-04

申请号：US17323170

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Julien Borrel

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732 ,  H01L21/265

Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

公开(公告)号：US11610813B2

公开(公告)日：2023-03-21

申请号：US17488714

申请日：2021-09-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Magali Gregoire

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.

公开(公告)号：US11604371B2

公开(公告)日：2023-03-14

申请号：US17661356

申请日：2022-04-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles Baudot

IPC: G02F1/025 ,  G02F1/01 ,  G02F1/017 ,  G02F1/225 ,  H01L21/02 ,  B82Y20/00

Abstract: In one embodiment, an electro-optical modulator includes a waveguide having a first major surface and a second major surface opposite the first major surface. A cavity is disposed in the waveguide. Multiple quantum wells are disposed in the cavity.

公开(公告)号：US20230071932A1

公开(公告)日：2023-03-09

申请号：US17885960

申请日：2022-08-11

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent SIMONY ,  Frederic LALANNE

IPC: H01L27/146

Abstract: An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.