公开(公告)号：US09929720B2

公开(公告)日：2018-03-27

申请号：US14847900

申请日：2015-09-08

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Thomas Quemerais ,  Alice Bossuet ,  Daniel Gloria

IPC: G01R1/067 ,  H03H11/24 ,  H03F3/60

CPC classification number: H03H11/245 ,  G01R1/06711 ,  H03F3/602 ,  H03F2200/211

Abstract: An attenuator includes: a first circuit including a common collector or common drain amplifier formed of a first transistor having its control node connected to an input of the attenuator and its emitter or source connected to an intermediate node of the attenuator; and a second circuit including a common collector or common drain amplifier formed of a second transistor having its emitter or source connected to the intermediate node and its control node connected to an output of the attenuator.

公开(公告)号：US20180083603A1

公开(公告)日：2018-03-22

申请号：US15462494

申请日：2017-03-17

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pascal Urard ,  Alok Kumar Tripathi

IPC: H03K3/356 ,  H03K19/00

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/02335 ,  H03K3/35625 ,  H03K19/0002

Abstract: The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.

公开(公告)号：US09899366B2

公开(公告)日：2018-02-20

申请号：US15096975

申请日：2016-04-12

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat ,  Jean Jimenez

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/74 ,  H01L29/744 ,  H01L29/10

CPC classification number: H01L27/0251 ,  H01L27/0262 ,  H01L29/1095 ,  H01L29/7436 ,  H01L29/744

Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.

公开(公告)号：US09899217B2

公开(公告)日：2018-02-20

申请号：US14555897

申请日：2014-11-28

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Shay Reboh ,  Yves Morand ,  Hubert Moriceau

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L21/265 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02689 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02686 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/78654 ,  H01L29/78684

Abstract: A method is provided for producing a microelectronic device provided with different strained areas in a superficial layer of a semi-conductor on insulator type substrate, including amorphizing a region of the superficial layer and then a lateral recrystallization of the region from crystalline areas adjoining the region.

公开(公告)号：US20170356938A1

公开(公告)日：2017-12-14

申请号：US15357244

申请日：2016-11-21

Applicant: STMicroelectronics SA

Inventor： Bruno Delplanque

IPC: G01R22/10 ,  H04L7/00

CPC classification number: G01R22/10 ,  G01R21/133 ,  G01R31/31721 ,  G01R31/31727 ,  G06F1/324 ,  H04L7/0008

Abstract: A reference clock signal of at least one module clock signal associated with each module is delivered. A measurement period is generated and a module whose consumption is to be determined is selected. The frequency of the at least one module clock signal associated with the selected module reduced during the measurement period. A measurement of a first consumption of the device is made in the measurement period. A measurement of a second consumption of the device is made outside the measurement period. The consumption of the selected module is determined from the first and measured first and second consumptions.

公开(公告)号：US09755610B2

公开(公告)日：2017-09-05

申请号：US14981189

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

IPC: H01F27/28 ,  H01F5/00 ,  H01F21/02 ,  H01F21/12 ,  H01F7/06 ,  H04B1/40 ,  H03H7/42 ,  H01F27/38 ,  H01L23/522 ,  H01F27/29 ,  H01F27/40 ,  H04W88/02

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US09735772B2

公开(公告)日：2017-08-15

申请号：US14865618

申请日：2015-09-25

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alexandre Dray ,  Emmanuel Josse

IPC: H01L25/00 ,  H03K17/687 ,  H01L21/66 ,  G01R31/28 ,  H01L27/02

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

公开(公告)号：US20170186623A1

公开(公告)日：2017-06-29

申请号：US15390077

申请日：2016-12-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas POSSEME ,  Maxime Garcia-Barros ,  Yves Morand

IPC: H01L21/324 ,  H01L21/322 ,  H01L29/78 ,  H01L21/02 ,  H01L21/447 ,  H01L21/762 ,  H01L21/223

CPC classification number: H01L21/324 ,  H01L21/02057 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/31155 ,  H01L21/3221 ,  H01L21/447 ,  H01L21/762 ,  H01L21/823468 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7827

Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

公开(公告)号：US20170179250A1

公开(公告)日：2017-06-22

申请号：US14973825

申请日：2015-12-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US09660034B1

公开(公告)日：2017-05-23

申请号：US15229746

申请日：2016-08-05

Applicant: STMicroelectronics SA

Inventor： Philippe Galy

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/1083 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/7838 ,  H01L29/78648

Abstract: An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.