公开(公告)号：US20180039531A1

公开(公告)日：2018-02-08

申请号：US15231251

申请日：2016-08-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel I. Lowell ,  Manish Gupta

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0763 ,  G06F9/30021 ,  G06F9/30101 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3887 ,  G06F11/0721 ,  G06F11/0784

Abstract: Techniques for performing redundant multi-threading (“RMT”) include the use of an RMT compare instruction by two program instances (“work-items”). The RMT compare instruction specifies a value from each work-item to be compared. Upon executing the RMT compare instructions, the work-items transmit the values to a hardware comparator unit. The hardware comparator unit compares the received values and performs an error action if the values do not match. The error action may include sending an error code in a return value back to the work-items that requested the comparison or emitting a trap signal. Optionally, the work-items also send addresses for comparison to the comparator unit. If the addresses and values match, then the comparator stores the value at the specified address. If either or both of the values or the addresses do not match, then the comparator performs an error action.

公开(公告)号：US20180018419A1

公开(公告)日：2018-01-18

申请号：US15207691

申请日：2016-07-12

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Omid Rowhani ,  Ioan Cordos ,  Kerry Hamel ,  Donald Clay

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F2217/02 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

公开(公告)号：US20180018291A1

公开(公告)日：2018-01-18

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US20180018242A1

公开(公告)日：2018-01-18

申请号：US15207943

申请日：2016-07-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Taniya Siddiqua ,  Vilas Sridharan

IPC: G06F11/14 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G06F2201/805 ,  G06F2201/84

Abstract: Methods and apparatus presented herein provide distributed checkpointing in a multi-node system, such as a network of servers in a data center. When checkpointing of application state data is needed in a node, the methods and apparatus determine whether checkpoint memory space is available in the node for checkpointing the application state data. If not enough checkpoint memory space is available in the node, the methods and apparatus request and find additional checkpoint memory space from other nodes in the system. In this manner, the methods and apparatus can checkpoint the application state data into available checkpoint memory spaces distributed among a plurality of nodes. This allows for high bandwidth and low latency checkpointing operations in the multi-node system.

公开(公告)号：US09870473B2

公开(公告)日：2018-01-16

申请号：US14529278

申请日：2014-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Denis Rystsov ,  Sebastien Nussbaum

IPC: H04L29/06 ,  G06F21/57 ,  G06F21/50 ,  G06F1/26 ,  G06F21/81 ,  G06F1/32

CPC classification number: G06F21/57 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3287 ,  G06F21/50 ,  G06F21/81 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/128 ,  Y02D10/171

Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.

公开(公告)号：US20180011798A1

公开(公告)日：2018-01-11

申请号：US15695683

申请日：2017-09-05

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony ASARO ,  Kevin NORMOYLE ,  Mark HUMMEL

IPC: G06F12/06 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0284 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1012 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

公开(公告)号：US20170373955A1

公开(公告)日：2017-12-28

申请号：US15192764

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Indrani Paul

IPC: H04L12/26

CPC classification number: G06F11/30 ,  G06F9/4893 ,  G06F2209/5019 ,  Y02D10/24

Abstract: Systems, apparatuses, and methods for achieving balanced execution in a multi-node cluster through runtime detection of performance variation are described. During a training phase, performance counters and an amount of time spent waiting for synchronization is monitored for a plurality of tasks for each node of the multi-node cluster. These values are utilized to generate a model which correlates the values of the performance counters to the amount of time spent waiting for synchronization. Once the model is built, the values of the performance counters are monitored for a period of time at the start of each task, and these values are input into the model. The model generates a prediction of whether a given node is on the critical path. If the given node is predicted to be on the critical path, the power allocation of the given node is increased.

公开(公告)号：US20170371784A1

公开(公告)日：2017-12-28

申请号：US15192542

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan R. Alsop ,  Bradford Beckmann

IPC: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/6042

Abstract: A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.

公开(公告)号：US20170371665A1

公开(公告)日：2017-12-28

申请号：US15191257

申请日：2016-06-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mauricio Breternitz ,  Mayank Daga

IPC: G06F9/30

Abstract: Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means clustering algorithm, the processor determines that a first plurality of data points belong to a first group during a given iteration. If the first plurality of data points is not an integer multiple of the number of processing lanes, then the processor reassigns a first number of data points from the first plurality of data points to one or more other groups. The processor then performs the next iteration with these first number of data points assigned to other groups even though the first number of data points actually meets the algorithmic criteria for belonging to the first group.

公开(公告)号：US09851777B2

公开(公告)日：2017-12-26

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.