公开(公告)号：US20170357587A1

公开(公告)日：2017-12-14

申请号：US15180806

申请日：2016-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： William Evan Jones, III

IPC: G06F12/0862 ,  G06F12/0842

CPC classification number: G06F12/0862 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/6026

Abstract: In a processing system comprising a cache, a method includes monitoring demand cache accesses for a thread to maintain a first running count of a number of times demand cache accesses for the thread are directed to cachelines that are adjacent in a first direction to cachelines that are targets of a set of sampled cache accesses for the thread. In response to determining the first running count has exceeded a first threshold, the method further includes enabling a first prefetching mode in which a received demand cache access for the thread triggers a prefetch request for a cacheline adjacent in the first direction to a cacheline targeted by the received demand cache access.

公开(公告)号：US20170357583A1

公开(公告)日：2017-12-14

申请号：US15181415

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Boyer ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/0804 ,  G06F12/0842 ,  G06F12/0806

CPC classification number: G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/502 ,  G06F2212/70

Abstract: Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.

公开(公告)号：US20170357509A1

公开(公告)日：2017-12-14

申请号：US15181837

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Akanksha Jain ,  Wei Huang ,  Indrani Paul

IPC: G06F9/30 ,  G06F1/32

CPC classification number: G06F9/30181 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F11/30

Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

公开(公告)号：US09837398B1

公开(公告)日：2017-12-05

申请号：US15360168

申请日：2016-11-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Omid Rowhani ,  Jason P. Cain ,  Ioan Cordos ,  Michael Davinson Sherriff ,  Hoang Q. Dao

IPC: H01L27/118 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

公开(公告)号：US20170345512A1

公开(公告)日：2017-11-30

申请号：US15267092

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov

IPC: G11C16/34 ,  G11C16/10 ,  G06F3/06 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/10 ,  G11C16/26

Abstract: A non-volatile memory device having at least one non-volatile flash memory formatted with physical addresses to read and write data that is organized into blocks of data, wherein the blocks of data are organized into pages of data, and wherein the pages of data are organized into cells of data. The non-volatile memory device includes a non-volatile memory controller to direct read and write requests to the non-volatile flash memory for the storage and retrieval of data. The non-volatile memory controller includes a flash translation layer to correlate read and write requests for data having a logical address between the reading and writing the data to physical address location of the non-volatile flash memory. The flash translation layer, when writing to a physical address location, chooses between a wear-leveling circuit and a wear-limiting circuit to select the physical address location.

公开(公告)号：US20170344421A1

公开(公告)日：2017-11-30

申请号：US15168045

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0411

Abstract: A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ECC) bits. The first error counter counts errors in the returned data, and provides a control signal in response to reaching a predetermined state. The scrubber controls the memory channel controller to read data sequentially and periodically from a plurality of addresses of a memory system, and in response to detecting a correctable error, to rewrite corrected data. The data processor is responsive to the control signal to perform a post package repair operation with the memory system in response to the control signal.

公开(公告)号：US09825843B2

公开(公告)日：2017-11-21

申请号：US14715023

申请日：2015-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: H01L25/065 ,  H01L23/498 ,  H04L12/755 ,  G06F17/50 ,  H01L23/48 ,  H01L23/538 ,  H04L12/701 ,  H01L25/18

CPC classification number: H04L45/021 ,  G06F17/5068 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/1461 ,  H01L2924/15192 ,  H04L45/00 ,  H01L2924/00

Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.

公开(公告)号：US20170332096A1

公开(公告)日：2017-11-16

申请号：US15170103

申请日：2016-06-01

Applicant: Advanced Micro Devices, Inc. ,  ATI TECHNOLOGIES ULC

Inventor： Kismat Singh ,  Kadagattur Gopinatha Srinidhi ,  Mark Chan ,  Neelakanth Devappa Shigihalli ,  Kishor Kayyar Lakshminarayana

IPC: H04N19/52 ,  H04N19/182 ,  H04N19/176 ,  H04N19/184 ,  H04N19/172

CPC classification number: H04N19/42 ,  H04N19/162 ,  H04N19/172 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/46 ,  H04N19/48

Abstract: A video codec includes a stitching module configured to select stored encoded video frames that are to be composed into a concatenated frame for display. The stitching module arranges the selected encoded video frames into a specified pattern, and stitches the arranged encoded video frames together to generate a stitched encoded frame. A decoder of the video codec then decodes the stitched encoded frame to generate the frame for display. By stitching together the encoded video frames prior to decoding, the video codec reduces the number of times the decoder must be initialized,

公开(公告)号：US20170315932A1

公开(公告)日：2017-11-02

申请号：US15139923

申请日：2016-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Moyer

IPC: G06F12/123 ,  G06F12/0862

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/602

Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.

公开(公告)号：US09806908B2

公开(公告)日：2017-10-31

申请号：US14620342

申请日：2015-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael E. James

IPC: H04L12/28 ,  H04L12/64

CPC classification number: H04L12/6418

Abstract: Each compute node of a cluster compute server generates and maintains route information for routing messages to other nodes of the server. Each compute node identifies the other nodes connected to a fabric interconnect and generates, based on a set of routing constraints, routes to each of the other nodes. Each compute node communicates messages to other nodes of the server via the generated routes. Because the routes are generated at each compute node the processing load to generate the routes is distributed among the compute nodes.