Filtering of noisy images
    72.
    发明申请
    Filtering of noisy images 有权
    过滤嘈杂的图像

    公开(公告)号:US20050276510A1

    公开(公告)日:2005-12-15

    申请号:US11148850

    申请日:2005-06-08

    Abstract: A method for correcting an image from defects and filtering from Gaussian noise corrects each pixel of the image when it is considered defective and filters it from Gaussian noise in one-pass. The one-pass improves the speed for performing the correcting and filtering. The drawbacks associated with choosing incompatible defect correction and filtering operations are overcome.

    Abstract translation: 一种从缺陷中校正图像并从高斯噪声滤波的方法,在被认为有缺陷的情况下校正图像的每个像素,并在一次通过时从高斯噪声中对其进行滤波。 单程提高了执行校正和过滤的速度。 克服了选择不兼容的缺陷校正和过滤操作相关的缺点。

    Circuit for selecting/deselecting a bitline of a non-volatile memory
    73.
    发明申请
    Circuit for selecting/deselecting a bitline of a non-volatile memory 有权
    用于选择/取消选择非易失性存储器的位线的电路

    公开(公告)号:US20050249022A1

    公开(公告)日:2005-11-10

    申请号:US11120766

    申请日:2005-05-03

    CPC classification number: G11C16/24

    Abstract: A bit-line selection circuit for a memory device includes a decoding line and a dummy line. The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal. The regulating circuit compensates for differences between the programming voltage and the reference voltage.

    Abstract translation: 用于存储器件的位线选择电路包括解码线和虚拟线。 解码线位于调节电压节点和产生存储器件中的单元的编程电压的编程电压节点之间。 解码线包括连接到调节电压节点的至少一个输入晶体管,并由使能/禁止信号控制。 虚拟线与解码线相同,并由使能/禁止信号控制。 在解码线和虚拟线之间连接均衡电路,用于将虚拟线路中的电流设置为与解码线中的电流相等。 调节电路调节在解码行中编程电压节点处产生的编程电压。 调节电路具有用于接收参考电压的第一输入端,用于接收虚拟线路中的编程电压节点上的检测电压的第二输入端和用于提供使能/禁止信号的输出端。 调节电路补偿编程电压和参考电压之间的差异。

    Driven circuit of an emitter switching configuration to control the saturation level of a power transistor when used with highly variable collector currents
    74.
    发明申请
    Driven circuit of an emitter switching configuration to control the saturation level of a power transistor when used with highly variable collector currents 有权
    发射极开关配置的驱动电路,用于控制功率晶体管在高可变集电极电流下的饱和电平

    公开(公告)号:US20050194623A1

    公开(公告)日:2005-09-08

    申请号:US11066610

    申请日:2005-02-25

    CPC classification number: H03K17/603 H03K17/567

    Abstract: A drive circuit for an emitter switching configuration of transistors having a cascode connection of a power bipolar transistor and of a power MOS transistor control the saturation level of the configuration in applications which provide highly variable collector currents. The drive circuit includes a circuit operable to apply a varying voltage value to the control terminal of the bipolar transistor. A current/voltage converter senses a collector current flowing in the power bipolar transistor and controls conduction of a first transistor responsive thereto, the conduction of the first transistor controlling the conduction of a second transistor so as to vary the control terminal voltage in proportion to the sensed collector current of the power bipolar transistor.

    Abstract translation: 具有功率双极晶体管和功率MOS晶体管的共源共栅连接的晶体管的发射极开关配置的驱动电路在提供高度可变的集电极电流的应用中控制该配置的饱和电平。 驱动电路包括可操作以将变化的电压值施加到双极晶体管的控制端的电路。 电流/电压转换器感测在功率双极晶体管中流动的集电极电流,并且响应于此控制第一晶体管的导通,第一晶体管的导通控制第二晶体管的导通,从而与控制端电压成比例地改变控制端电压 感测功率双极晶体管的集电极电流。

    Optical module including an optoelectronic device
    75.
    发明申请
    Optical module including an optoelectronic device 有权
    光模块包括光电器件

    公开(公告)号:US20050163435A1

    公开(公告)日:2005-07-28

    申请号:US11015363

    申请日:2004-12-17

    Inventor: Antonio Fincato

    CPC classification number: G02B6/4214 G02B6/4292

    Abstract: An optical module includes a support substrate, and an optoelectronic device on the support substrate. A coupling device provides optical coupling of the optoelectronic device with an optical fiber. The coupling device is integrated in the substrate, and is a reflection device inserted into an optical path between the optoelectronic device and the optical fiber.

    Abstract translation: 光学模块包括支撑衬底和支撑衬底上的光电器件。 耦合装置提供光电子器件与光纤的光耦合。 耦合器件集成在衬底中,并且是插入到光电子器件和光纤之间的光路中的反射器件。

    System for controlling the speed of a voice coil motor (VCM) in order to provide a low noise ramp loading of a hard disk head
    76.
    发明申请
    System for controlling the speed of a voice coil motor (VCM) in order to provide a low noise ramp loading of a hard disk head 有权
    用于控制音圈电机(VCM)的速度的系统,以便提供硬盘头的低噪声斜坡加载

    公开(公告)号:US20050157418A1

    公开(公告)日:2005-07-21

    申请号:US11019937

    申请日:2004-12-21

    Applicant: Ezio Galbiati

    Inventor: Ezio Galbiati

    CPC classification number: G11B21/12

    Abstract: A system controls the speed of a Voice Coil Motor (VCM) in order to perform the ramp loading of hard disk heads with low noise. This system includes a generator for generating a discontinuous PWM drive signal to a power stage. A sampling block is clocked by a synchronization signal issued from the generator and receives as an input a signal related to the electromotive force (Bemf) provided by the VCM motor. An adder node placed at the sampling block output receives a signal related to a reference electromotive force (Bemf_ref). A filtering block placed downstream of the adder node generates a power supply voltage signal to the power stage. The control system further includes a control block having at least one voltage divider and controlled switches. The control block is input the signal issued from the filtering block and control signals from the generator block to selectively operate the controlled switches and set the value of the power-on signal of the power stage.

    Abstract translation: 系统控制音圈电机(VCM)的速度,以便执行低噪声硬盘磁头的斜坡加载。 该系统包括用于产生到功率级的不连续PWM驱动信号的发生器。 采样块由发生器发出的同步信号提供时钟,并接收与VCM电机提供的电动势(Bemf)相关的信号作为输入。 放置在采样块输出处的加法器节点接收与参考电动势(Bemf_ref)相关的信号。 放置在加法器节点下游的滤波块产生到功率级的电源电压信号。 控制系统还包括具有至少一个分压器和受控开关的控制块。 控制块输入从滤波块发出的信号和来自发生器模块的控制信号,以选择性地操作受控开关并设置功率级的通电信号的值。

    Power on reset device
    78.
    发明申请
    Power on reset device 有权
    上电复位设备

    公开(公告)号:US20050141250A1

    公开(公告)日:2005-06-30

    申请号:US11019927

    申请日:2004-12-21

    CPC classification number: H02M1/081 H02M1/32 H02M3/33592 Y02B70/1475

    Abstract: A power conversion device includes a first and second input terminal for connection to a transformer winding and at least an output terminal. A first and second synchronous rectifier are associated with the first and second input terminals, respectively. An inductor within an output stage is connected between the first input terminal and the output terminal. A driving circuit includes first and second output terminals connected to respective control terminals of the first and second synchronous rectifiers. An adjustable threshold control block is connected between the first and second input terminals and is connected to the inductor. The control block is enabled responsive to a control signal on the first output terminal of the driving circuit. The control block operates to clamp the voltage of the first input terminal to a preset value during at least a dead time period of the device operation.

    Abstract translation: 电力转换装置包括用于连接到变压器绕组和至少输出端子的第一和第二输入端子。 第一和第二同步整流器分别与第一和第二输入端相关联。 输出级内的电感器连接在第一输入端和输出端之间。 驱动电路包括连接到第一和第二同步整流器的相应控制端的第一和第二输出端。 可调阈值控制块连接在第一和第二输入端之间,并连接到电感器。 控制块响应于驱动电路的第一输出端上的控制信号使能。 控制块用于在设备操作的至少死区时间段期间将第一输入端子的电压钳位到预设值。

    Method and system for de-interlacing digital images, and computer program product therefor
    79.
    发明申请
    Method and system for de-interlacing digital images, and computer program product therefor 有权
    去隔行数字图像的方法和系统,以及计算机程序产品

    公开(公告)号:US20050110901A1

    公开(公告)日:2005-05-26

    申请号:US10925884

    申请日:2004-08-24

    CPC classification number: H04N7/014 H04N7/012 H04N7/0142

    Abstract: To carry out de-interlacing of digital images there is provided a spatial-type de-interlacing process to be applied to a digital image for obtaining a spatial reconstruction. Furthermore, to the digital image there are also applied one or more temporal-type de-interlacing processes for obtaining one or more temporal reconstructions, and the spatial reconstruction and the one or more temporal reconstructions are sent to a decision module. The decision module applies a cost function to the spatial reconstruction and the temporal reconstructions and chooses from among the spatial reconstruction and the temporal reconstructions the one that minimizes the cost function. Preferential application is to display systems, in particular displays of a cathode-ray type, liquid-crystal type, and plasma type which use a mechanism of progressive scan.

    Abstract translation: 为了执行数字图像的去隔行,提供了一种应用于数字图像以获得空间重建的空间类型去隔行处理。 此外,对于数字图像,还应用一个或多个时间型去隔行处理来获得一个或多个时间重建,并且空间重建和一个或多个时间重建被发送到决策模块。 决策模块将成本函数应用于空间重建和时间重建,并从空间重建和时间重建中选择最小化成本函数的重建。 优选应用是显示系统,特别是使用逐行扫描机制的阴极射线型,液晶型和等离子型显示器。

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