-
71.发明授权公开(公告)号：US07132718B2
公开(公告)日：2006-11-07
申请号：US10726507
申请日：2003-12-04
Applicant: Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
Inventor： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC: H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC classification number: H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在选择栅极的两侧的区域和p型阱的存储栅极中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。
-
公开(公告)号：US20050265080A1
公开(公告)日：2005-12-01
申请号：US11137518
申请日：2005-05-26
Applicant: Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
Inventor： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
CPC classification number: G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
Abstract translation: 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。
-
73.发明申请公开(公告)号：US20050199940A1
公开(公告)日：2005-09-15
申请号：US11013406
申请日：2004-12-17
Applicant: Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
Inventor： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
IPC: H01L21/8247 , H01L27/115 , H01L29/04 , H01L29/788 , H01L29/792
CPC classification number: H01L21/28282 , H01L27/11568 , H01L29/792
Abstract: A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.
Abstract translation: 分离栅结构的MONOS非易失性存储器分别由热电子和热孔执行写入和擦除，容易导致电子不被擦除并且保留在选择栅电极侧壁上的氮化硅膜中，并且结果 在改写耐久性的恶化。 当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。 在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。
-
公开(公告)号：US20050176202A1
公开(公告)日：2005-08-11
申请号：US11005015
申请日：2004-12-07
Applicant: Digh Hisamoto , Kan Yasui
Inventor： Digh Hisamoto , Kan Yasui
IPC: H01L21/8247 , H01L21/00 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC classification number: H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L29/66825
Abstract: A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.
Abstract translation: 提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。 当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。 因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。
-
75.发明申请公开(公告)号：US20050095960A1
公开(公告)日：2005-05-05
申请号：US11004991
申请日：2004-12-07
Applicant: Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
Inventor： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
CPC classification number: B24B53/017 , B24B37/042 , B24B41/04 , B24B53/12
Abstract: The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.
Abstract translation: 本发明涉及一种抛光装置以及使用该装置的半导体制造方法。 磨石表面的磨合通过施胶处理进行研磨，由此可以进行工具表面的修整，同时防止在磨石表面产生裂纹，这是产生划痕的原因。 此外，可以保证修整工具的表面的平整度，因为切割的尺寸大小; 即使使用了几厘米厚的砂轮，也可以保持平坦度， 并且可以总是执行具有较少的面内不均匀性的处理。 因此，修整工具的寿命可以大大延长。 此外，与晶片的处理联合进行本施胶修整，从而能够提高装置的生产量以及维持处理速度。 本装置和方法对于具有不规则性的各种衬底表面的平坦化是有效的。
-
Patent Agency Ranking
76.发明授权Method for fabricating semiconductor device and processing apparatus for processing semiconductor device 失效半导体装置的制造方法以及半导体装置的处理装置公开(公告)号：US06612912B2
公开(公告)日：2003-09-02
申请号：US09371003
申请日：1999-08-10
Applicant: Kan Yasui , Souichi Katagiri , Shigeo Moriyama , Yoshio Kawamura , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato
Inventor： Kan Yasui , Souichi Katagiri , Shigeo Moriyama , Yoshio Kawamura , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato
IPC: B24B100
CPC classification number: B24B53/017 , B24B1/04 , B24B37/042 , B24B53/12
Abstract: A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.
Abstract translation: 一种制造半导体器件的方法包括：当半导体晶片的凹凸图案通过使用由晶片保持器保持的半导体晶片进行平面化而进行的刷子或超声波的磨石表面激活处理， 磨料颗粒和用于保持磨料颗粒的材料，半导体晶片被相对运动地压在其上。 半导体晶片以高去除率进行处理，并且精确地控制抛光厚度。
-
77.发明授权公开(公告)号：US08373943B2
公开(公告)日：2013-02-12
申请号：US12941953
申请日：2010-11-08
Applicant: Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
Inventor： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
IPC: G11B5/127
CPC classification number: G11B5/398 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/02 , G11B5/1278 , G11B5/3146 , G11B5/3163 , G11B5/3906 , G11B2005/0002 , G11B2005/0024 , H01F10/3254 , H01F10/3263 , H01F10/329
Abstract: According to one embodiment, a method for producing a magnetic head includes depositing a first film above a substrate, etching a pattern into the first film, depositing a second film on the etched portion of the first film, and depositing a third film above the first and second film to form a multilayer magnetic film, wherein the second film is embedded between the first and third film in a portion of the first film that is removed. In another embodiment, a differential magnetic read head includes a magnetic multilayer film comprising a stack of a first magnetic sensor film and a second magnetic sensor film which are not magnetically connected and a hard magnetic film provided on both sides in a track width direction of the magnetic multilayer film for controlling a magnetic domain of the magnetic multilayer film. The hard magnetic film is a laminated structure as described above.
Abstract translation: 根据一个实施例，一种用于制造磁头的方法包括在基板上沉积第一膜，将图案蚀刻到第一膜中，在第一膜的蚀刻部分上沉积第二膜，以及在第一膜上沉积第三膜 和第二膜以形成多层磁性膜，其中第二膜在被去除的第一膜的一部分中嵌入第一和第三膜之间。 在另一个实施例中，差分磁读头包括磁性多层膜，该磁性多层膜包括不磁性连接的第一磁性传感器膜和第二磁性传感器膜的叠层，以及设置在第二磁性传感器膜的轨道宽度方向上的两侧的硬磁性膜 用于控制磁性多层膜的磁畴的磁性多层膜。 硬磁性膜是如上所述的层叠结构。
-
78.发明授权公开(公告)号：US08223464B2
公开(公告)日：2012-07-17
申请号：US12615221
申请日：2009-11-09
Applicant: Kan Yasui , Masato Shiimoto , Takeshi Nakagawa , Hiroyuki Katada , Nobuo Yoshida , Hiroyuki Hoshiya
Inventor： Kan Yasui , Masato Shiimoto , Takeshi Nakagawa , Hiroyuki Katada , Nobuo Yoshida , Hiroyuki Hoshiya
CPC classification number: G11B5/3163 , G11B5/398
Abstract: In one embodiment, a differential-type magnetic read head includes a differential-type magneto-resistive-effect film formed on a substrate, and a pair of electrodes for applying current in a direction perpendicular to a film plane of the film. The film includes a first and second stacked film, each having a pinned layer, an intermediate layer, and a free layer, with the second stacked film being formed on the first stacked film. A side face in a track width direction of the film is shaped to have an inflection point at an intermediate position in a thickness direction of the film, and the side face is shaped to be approximately vertical to the substrate in an upward direction of the substrate from the inflection point. Also, the side face is shaped to be gradually increased in track width as approaching the substrate in a downward direction of the substrate from the inflection point.
Abstract translation: 在一个实施例中，差分型磁读头包括形成在基板上的差分型磁阻效应膜和用于在垂直于膜的膜平面的方向上施加电流的一对电极。 膜包括第一和第二堆叠膜，每个具有钉扎层，中间层和自由层，第二堆叠膜形成在第一堆叠膜上。 膜的轨道宽度方向的侧面成形为在膜的厚度方向上的中间位置具有拐点，并且侧面成形为在基板的上方大致垂直于基板 从拐点。 此外，侧面被成形为在从拐点向基板向下方向接近基板的轨迹宽度上逐渐增加。
-
79.发明申请公开(公告)号：US20110134564A1
公开(公告)日：2011-06-09
申请号：US12957229
申请日：2010-11-30
Applicant: Nobuo Yoshida , Masato Shiimoto , Kenichi Akita , Kan Yasui
Inventor： Nobuo Yoshida , Masato Shiimoto , Kenichi Akita , Kan Yasui
CPC classification number: H01L43/08 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/3912 , G11B5/398
Abstract: A magnetic head, according to one embodiment, includes a sensor film, a sensor cap film provided above the sensor film, a pair of shields including an upper magnetic shield and a lower magnetic shield which serve as electrodes that pass current in a film thickness direction of the sensor film, a track insulating film contacting both sides of the sensor film in the track width direction, a graded domain control film arranged on both sides in the track width direction of the sensor film adjacent the track insulating film, and an element height direction insulating film positioned on an opposite side of the sensor film relative to an air-bearing surface, wherein an edge position of the element height direction insulating film adjacent the sensor film on the air-bearing surface side is substantially the same as an edge position of the sensor cap film in the element height direction.
Abstract translation: 根据一个实施例的磁头包括传感器膜，设置在传感器膜上方的传感器盖膜，包括上磁屏蔽和下磁屏蔽的一对屏蔽件，其用作使电流在膜厚度方向上通过的电极 传感器膜的传感器膜的两侧接触的轨道绝缘膜，布置在邻近轨道绝缘膜的传感器膜的轨道宽度方向两侧的梯度控制膜和元件高度 相对于空气轴承表面定位在传感器膜的相对侧上的方向绝缘膜，其中与空气轴承表面侧相邻的传感器膜的元件高度方向绝缘膜的边缘位置与边缘位置基本相同 传感器盖膜在元件高度方向上。
-
80.发明申请公开(公告)号：US20110116184A1
公开(公告)日：2011-05-19
申请号：US12941953
申请日：2010-11-08
Applicant: Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
Inventor： Kan Yasui , Nobuo Yoshida , Katsuro Watanabe , Norihiro Okawa
CPC classification number: G11B5/398 , B82Y25/00 , G01R33/093 , G01R33/098 , G11B5/02 , G11B5/1278 , G11B5/3146 , G11B5/3163 , G11B5/3906 , G11B2005/0002 , G11B2005/0024 , H01F10/3254 , H01F10/3263 , H01F10/329
Abstract: According to one embodiment, a method for producing a magnetic head includes depositing a first film above a substrate, etching a pattern into the first film, depositing a second film on the etched portion of the first film, and depositing a third film above the first and second film to form a multilayer magnetic film, wherein the second film is embedded between the first and third film in a portion of the first film that is removed. In another embodiment, a differential magnetic read head includes a magnetic multilayer film comprising a stack of a first magnetic sensor film and a second magnetic sensor film which are not magnetically connected and a hard magnetic film provided on both sides in a track width direction of the magnetic multilayer film for controlling a magnetic domain of the magnetic multilayer film. The hard magnetic film is a laminated structure as described above.
Abstract translation: 根据一个实施例，一种用于制造磁头的方法包括在基板上沉积第一膜，将图案蚀刻到第一膜中，在第一膜的蚀刻部分上沉积第二膜，以及在第一膜上沉积第三膜 和第二膜以形成多层磁性膜，其中第二膜在被去除的第一膜的一部分中嵌入第一和第三膜之间。 在另一个实施例中，差分磁读头包括磁性多层膜，该磁性多层膜包括不磁性连接的第一磁性传感器膜和第二磁性传感器膜的叠层，以及设置在第二磁性传感器膜的轨道宽度方向上的两侧的硬磁性膜 用于控制磁性多层膜的磁畴的磁性多层膜。 硬磁性膜是如上所述的层叠结构。
-
-
-
-
-
-
-
-
-
Search Results
100
records
(took 0.018 seconds)
