公开(公告)号：US09117527B2

公开(公告)日：2015-08-25

申请号：US14158116

申请日：2014-01-17

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki Kim

IPC: G11C16/04 ,  G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

Abstract translation: 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。

公开(公告)号：US08855277B2

公开(公告)日：2014-10-07

申请号：US13751825

申请日：2013-01-28

Applicant: MOSAID Technologies Incorporated

Inventor： Yehuda Binder

IPC: H04M11/00 ,  H04M11/06 ,  H04M7/00 ,  H04L12/28

CPC classification number: H04M7/0003 ,  H04L12/2803 ,  H04L12/2838 ,  H04L2012/2843 ,  H04L2012/2845 ,  H04L2012/285 ,  H04M11/062

Abstract: An outlet for coupling at least one data unit to digital data carried over wiring that simultaneously carry a packet-based serial digital data signal and a power signal over the same conductors. The outlet includes: a wiring connector for connecting to the wiring; a transceiver coupled to the wiring connector for transmitting and receiving packet-based serial digital data over the wiring; a LAN connector coupled to the transceiver for bi-directional packet-based data communication with at least one data unit; a bridge or a router coupled between the transceiver and the LAN connector for passing data bi-directionally between the at least one data unit and the wiring; and a single enclosure housing the above-mentioned components. The enclosure is mountable into a standard wall outlet receptacle or wall outlet opening, and the transceiver and the bridge or router are coupled to the wiring connector to be powered from the power signal.

Abstract translation: 用于将至少一个数据单元耦合到通过布线承载的数字数据的插座，其同时携带基于分组的串行数字数据信号和通过相同导体的功率信号。 插座包括：用于连接到接线的接线连接器; 耦合到布线连接器的收发器，用于通过布线发送和接收基于分组的串行数字数据; 耦合到收发器的LAN连接器，用于与至少一个数据单元的双向分组数据通信; 耦合在所述收发器和所述LAN连接器之间的桥或路由器，用于在所述至少一个数据单元和所述布线之间双向传递数据; 以及容纳上述部件的单个外壳。 外壳可安装到标准的墙壁插座或墙壁出口开口中，收发器和桥接器或路由器通过电源信号耦合到接线连接器供电。

公开(公告)号：US08817779B2

公开(公告)日：2014-08-26

申请号：US13956933

申请日：2013-08-01

Applicant: MOSAID Technologies Incorporated

Inventor： Yehuda Binder

IPC: H04L5/20 ,  H04M11/06 ,  H04B3/54 ,  H04L12/66

CPC classification number: H04L5/20 ,  H04B3/542 ,  H04L12/66 ,  H04L2012/6421 ,  H04L2012/6424 ,  H04L2012/644 ,  H04M11/062 ,  H04M11/066 ,  Y10S439/95 ,  Y10T307/297

Abstract: A device for enabling a local area network wiring structure to simultaneously carry digital data and analog telephone signals on the same transmission medium. It is particularly applicable to a network in star topology, in which remote data units (e.g. personal computers) are each connected to a hub through a cable comprising at least two pairs of conductors, providing a data communication path in each direction. Modules at each end of the cable provide a phantom path for telephony (voice band) signals between a telephone near the data set and a PBX, through both conductor pairs in a phantom circuit arrangement. All such communication paths function simultaneously and without mutual interference. The modules comprise simple and inexpensive passive circuit components.

Abstract translation: 一种用于使局域网布线结构能够在相同传输介质上携带数字数据和模拟电话信号的装置。 特别适用于星型拓扑网络，其中远程数据单元（例如，个人计算机）各自通过包括至少两对导体的电缆连接到集线器，从而在每个方向上提供数据通信路径。 电缆每端的模块通过虚拟电路布置中的两个导体对提供了数据集附近的电话和PBX之间的电话（语音频带）信号的幻像路径。 所有这些通信路径同时工作，没有相互干扰。 这些模块包括简单而廉价的无源电路组件。

公开(公告)号：US08767430B2

公开(公告)日：2014-07-01

申请号：US13957713

申请日：2013-08-02

Applicant: MOSAID Technologies Incorporated

Inventor： Peter Gillingham ,  Roland Schuetz

IPC: G11C5/02 ,  G11C5/00 ,  G11C5/06 ,  G11C8/00

CPC classification number: G11C5/025 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4243 ,  G11C16/04

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract translation: 可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。 每个MCD对具有与第二MCD通信的第一MCD。 每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。 响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。 环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

公开(公告)号：US20140179059A1

公开(公告)日：2014-06-26

申请号：US14193436

申请日：2014-02-28

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom PYEON

IPC: H01L21/82 ,  H01L23/00

CPC classification number: H01L21/82 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L24/37 ,  H01L24/40 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/24145 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/84

Abstract: An integrated circuit method is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.

Abstract translation: 集成电路方法具有封装级连接性，其内部电子电路与其封装衬底上的接触点之间，而不需要顶部金属焊盘或接合线。

公开(公告)号：US20140151774A1

公开(公告)日：2014-06-05

申请号：US13803085

申请日：2013-03-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub Rhie

IPC: H01L29/792 ,  H01L29/66

Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

Abstract translation: 公开了一种制造具有垂直单元堆栈结构的闪速存储器的方法。 该方法包括在具有离子注入阱的衬底的单元区域中形成源极线，并相对于源极线形成对准标记。 对准标记形成在基板的单元区域外的基板中。 在形成源极线之后，形成电池层叠层。 在形成电池堆叠层之后，使用对准标记在相对于先前形成的源极线的位置处形成电池堆叠层中的电池柱，以正确地定位电池柱。

公开(公告)号：US20140133235A1

公开(公告)日：2014-05-15

申请号：US14158116

申请日：2014-01-17

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki KIM

IPC: G11C16/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.

Abstract translation: 具有至少一个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小。 每个存储体包括至少两个具有对应页面缓冲器的存储器平面，其中响应于配置数据和地址数据，同时选择性地访问存储器层的任何数量和组合。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。 通过选择性地调整存储体的页面大小，相应地调整块大小。

公开(公告)号：US08724384B2

公开(公告)日：2014-05-13

申请号：US13777485

申请日：2013-02-26

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  William F. Petrie

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M−1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

公开(公告)号：US20140112074A1

公开(公告)日：2014-04-24

申请号：US13830135

申请日：2013-03-14

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Hyoung Seub RHIE

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C16/14

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract translation: 一种使用现有行解码电路的非易失性存储器件，用于选择性地向至少一个所选择的存储块提供全局擦除电压，以便于擦除所述至少一个所选存储块的所有非易失性存储单元。 更具体地，擦除电压耦合到至少一个所选存储块的存储器单元的单元体或衬底，其中单元体与至少一个其它存储块中的非易失性存储单元的单元体电隔离 。 通过将擦除电压路径与用于驱动所选存储器块的行信号的现有行解码电路进行积分，不需要额外的解码逻辑或电路来将擦除电压提供给至少一个所选择的存储块。

公开(公告)号：US20140104954A1

公开(公告)日：2014-04-17

申请号：US14107735

申请日：2013-12-16

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。