摘要:
An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.
摘要翻译:布置在集成电路基板上并具有降低的寄生电容的I / O电路。 I / O电路包括被分割成第一信号线段和第二信号线段的信号线,以及设置在第一和第二信号线段之间的感应结构。 片上终端元件耦合到第一信号线段,并且静电放电(ESD)元件耦合到第二信号线段。
摘要:
An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.
摘要:
An array oscillator circuit is disclosed herein. The array oscillator circuit includes a plurality of ring oscillators, each ring oscillator having a plurality of buffer stages for generating output signals on a like plurality of oscillator output ports. Interconnections are provided between each of the plurality of ring oscillators and at least one other of the plurality of ring oscillators such that the plurality of ring oscillators oscillate at identical frequencies and such that the output signals on the each ring oscillator's plurality of oscillator output ports have a phase offset from the signals generated on corresponding ones of the other ring oscillator's oscillator output ports. A multiplexer provides an electrical connection to a selected one of the plurality of oscillator output ports of the plurality of ring oscillators.
摘要:
A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnaround at one end of the data bus. The clockline ensures that clock and data signals travel in the same direction. Synchronization circuitry within transmitting devices synchronizes data signals to be coupled onto the data bus with the clock signal used by other devices to receive the data.
摘要:
A method and apparatus for testing input and output parameters for high speed integrated circuit devices. An integrated circuit tester generates a receive clock and a transmit clock using a pair of pre-selected output pins. The integrated circuit tester adjusts the phase relation between the transmit clock and the receive clock. Special circuitry within the device under test compares input and output data to detect errors.
摘要:
A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.
摘要:
Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the system constructs a calibration bit pattern for the signaling system that is based substantially on the ISI-residual. Finally, the system uses the calibration bit pattern to calibrate, optimize and determine an aspect of the performance of the signaling system.
摘要:
Digital images are computed using an approach for correcting lens aberration. According to an example embodiment of the present invention, a digital imaging arrangement implements microlenses to direct light to photosensors that detect the light and generate data corresponding to the detected light. The generated data is used to compute an output image, where each output image pixel value corresponds to a selective weighting and summation of a subset of the detected photosensor values. The weighting is a function of characteristics of the imaging arrangement. In some applications, the weighting reduces the contribution of data from photosensors that contribute higher amounts of optical aberration to the corresponding output image pixel.
摘要:
A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.
摘要:
Various approaches to imaging involve selecting directional and spatial resolution. According to an example embodiment, images are computed using an imaging arrangement to facilitate selective directional and spatial aspects of the detection and processing of light data. Light passed through a main lens is directed to photosensors via a plurality of microlenses. The separation between the microlenses and photosensors is set to facilitate directional and/or spatial resolution in recorded light data, and facilitating refocusing power and/or image resolution in images computed from the recorded light data. In one implementation, the separation is varied between zero and one focal length of the microlenses to respectively facilitate spatial and directional resolution (with increasing directional resolution, hence refocusing power, as the separation approaches one focal length).