公开(公告)号：US20240079079A1

公开(公告)日：2024-03-07

申请号：US18233257

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/00 ,  G11C29/02 ,  G11C29/52

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US11921650B2

公开(公告)日：2024-03-05

申请号：US18117119

申请日：2023-03-03

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G06F13/1668 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

公开(公告)号：US11921642B2

公开(公告)日：2024-03-05

申请号：US17986781

申请日：2022-11-14

Applicant: Rambus Inc.

Inventor： Trung Diep ,  Hongzhong Zheng

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G11C7/10

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G11C7/1072 ,  G06F2212/283 ,  G06F2212/656

Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

公开(公告)号：US11914508B2

公开(公告)日：2024-02-27

申请号：US17065082

申请日：2020-10-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

公开(公告)号：US11900985B1

公开(公告)日：2024-02-13

申请号：US17405527

申请日：2021-08-18

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Abhishek Desai

IPC: G11C11/4076 ,  G06F1/06 ,  H03K3/017

CPC classification number: G11C11/4076 ,  G06F1/06 ,  H03K3/017

Abstract: A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.

公开(公告)号：US11899597B2

公开(公告)日：2024-02-13

申请号：US17649773

申请日：2022-02-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/362 ,  G06F13/16 ,  G06F13/00 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/00 ,  G06F13/4243

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US11899571B2

公开(公告)日：2024-02-13

申请号：US17673277

申请日：2022-02-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G06F12/0292

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US20240036975A1

公开(公告)日：2024-02-01

申请号：US18230403

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

公开(公告)号：US11886375B2

公开(公告)日：2024-01-30

申请号：US17751480

申请日：2022-05-23

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: G06F13/42 ,  H04L1/20 ,  H04L1/00 ,  H04L1/24 ,  H04L5/14 ,  H04L25/02 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D30/50

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

公开(公告)号：US20240028207A1

公开(公告)日：2024-01-25

申请号：US18235068

申请日：2023-08-17

Applicant: Rambus Inc.

Inventor： David Wang ,  Nirmal Saxena

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F3/0611 ,  G06F13/1642 ,  G06F13/00 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.