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    Method for manufacturing semiconductor device
    71.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07763539B2

    公开(公告)日：2010-07-27

    申请号：US12262915

    申请日：2008-10-31

    申请人： Seung Hyun Kim

    发明人： Seung Hyun Kim

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L2221/1036 ,  H01L2221/1063

    摘要： A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surface of a transistor. Next, a trench and a contact hole are formed by etching the dielectric layer so that the upper surface of the transistor is exposed. Then, a contact is formed by embedding a first conductive layer in the contact hole. Next, an etching stop layer is selectively forming on an upper part of the contact. Then, the semiconductor device is blanket-etched such that the first conductive layer remains in the trench. Next, the etching stop layer is removed. Finally, a metal line is formed by embedding a second conductive layer in the trench.

    摘要翻译： 一种半导体器件的制造方法。 在一个示例性实施例中，制造半导体器件的方法包括各种步骤。 首先，在包括晶体管的上表面的半导体衬底的整个表面上形成电介质层。 接下来，通过蚀刻电介质层形成沟槽和接触孔，使晶体管的上表面露出。 然后，通过在接触孔中嵌入第一导电层形成接触。 接下来，在接触件的上部选择性地形成蚀刻停止层。 然后，半导体器件被覆盖蚀刻，使得第一导电层保留在沟槽中。 接下来，去除蚀刻停止层。 最后，通过在沟槽中嵌入第二导电层形成金属线。

    Metal Line of Semiconductor Device and Method of Manufacturing the Same
    72.
    发明申请
    Metal Line of Semiconductor Device and Method of Manufacturing the Same 失效
    半导体器件金属线及其制造方法

    公开(公告)号：US20080157371A1

    公开(公告)日：2008-07-03

    申请号：US11842851

    申请日：2007-08-21

    申请人： SEUNG HYUN KIM

    发明人： SEUNG HYUN KIM

    IPC分类号： H01L23/48 ,  H01L21/44

    CPC分类号： H01L23/53238 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are a metal line of a semiconductor device and a method of manufacturing the same. In one embodiment, the metal line includes a first interlayer dielectric layer pattern formed on a lower interconnection structure and having a via hole that exposes a lower interconnection of the lower interconnection structure, a first barrier pattern selectively covering a sidewall of the via hole and the lower interconnection, a second interlayer dielectric layer pattern on the first interlayer dielectric layer pattern and having a trench that exposes the via hole, a second barrier pattern covering an inner wall of the trench and the first barrier pattern, a seed pattern formed on the second barrier pattern, and a copper line formed on the seed pattern.

    摘要翻译： 公开了半导体器件的金属线及其制造方法。 在一个实施例中，金属线包括形成在下互连结构上并具有暴露下互连结构的下互连的通孔的第一层间介质层图案，选择性地覆盖通孔的侧壁的第一阻挡图案和 下互连，第一层间介质层图案上的第二层间介质层图案，并且具有暴露通孔的沟槽，覆盖沟槽的内壁和第一势垒图案的第二阻挡图案，形成在第二层 阻挡图案和形成在种子图案上的铜线。

    PASSIVATION LAYER FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    73.
    发明申请
    PASSIVATION LAYER FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
    半导体器件的钝化层及其制造方法

    公开(公告)号：US20070148987A1

    公开(公告)日：2007-06-28

    申请号：US11609897

    申请日：2006-12-12

    申请人： Seung Hyun Kim

    发明人： Seung Hyun Kim

    IPC分类号： H01L21/31 ,  H01L21/4763

    CPC分类号： H01L21/76829 ,  H01L21/31155 ,  H01L21/3144 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76825

    摘要： Embodiments relate to a passivation layer for a semiconductor device that may be formed in a substrate having a plurality of semiconductor devices. The passivation layer may includes a first passivation layer, a second passivation layer, and a third passivation layer, and the passivation layer may have a laminated triple layer structure.

    摘要翻译： 实施例涉及可以形成在具有多个半导体器件的衬底中的用于半导体器件的钝化层。 钝化层可以包括第一钝化层，第二钝化层和第三钝化层，并且钝化层可以具有层叠的三层结构。

    Methods of forming metal interconnection lines in semiconductor devices
    74.
    发明授权
    Methods of forming metal interconnection lines in semiconductor devices 有权
    在半导体器件中形成金属互连线的方法

    公开(公告)号：US07186641B2

    公开(公告)日：2007-03-06

    申请号：US11009470

    申请日：2004-12-10

    申请人： Seung Hyun Kim

    发明人： Seung Hyun Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76885

    摘要： A method of forming metal interconnection line for a semiconductor device being capable of forming a plug without voids irrespective of aspect ratios is provided. In one example, the method includes forming a first metal layer on a semiconductor substrate; forming a second metal layer on the first metal layer; forming the plugs by patterning the second metal layer; forming the lower metal interconnection lines by patterning the first metal layer; and forming an interlayer insulating layer having a planarized surface on the substrate to fill gaps between the lower metal lines and between the plugs.

    摘要翻译： 提供一种形成半导体器件的金属互连线的方法，其能够形成无空隙的插头，而与长宽比无关。 在一个实例中，该方法包括在半导体衬底上形成第一金属层; 在所述第一金属层上形成第二金属层; 通过图案化第二金属层形成插塞; 通过图案化第一金属层形成下金属互连线; 以及在基板上形成具有平坦化表面的层间绝缘层，以填充下金属线之间和插塞之间的间隙。

    Pellet of plant seed, a method of pelletization and a cultivation method of plants using the same
    75.
    发明申请
    Pellet of plant seed, a method of pelletization and a cultivation method of plants using the same 审中-公开
    植物种子颗粒，造粒方法和使用其的植物的培养方法

    公开(公告)号：US20060048446A1

    公开(公告)日：2006-03-09

    申请号：US10532642

    申请日：2003-09-16

    申请人： Seung-Hyun Kim

    发明人： Seung-Hyun Kim

    IPC分类号： A01C1/06

    CPC分类号： A01C1/06

    摘要： The present invention relates to a pelletization method of plant seed by mixing fertilizer, plant growth regulator, bactericide and insecticide with peatmoss, forming and drying said mixture, inserting the plant seed into it, pressing and sealing those and then obtaining the resulted pellet with plant seed. The present invention makes it possible to provide a pellet with plant seed being great in plant growing after germination by preventing physiological reaction of seed from removal of water. Also, the present invention can be us ed for bulbous plants and is not necessary to cover with earth on those after sowing seeds in a soil surface.

    摘要翻译： 本发明涉及通过将肥料，植物生长调节剂，杀菌剂和杀虫剂与泥炭混合，将所述混合物形成和干燥，将植物种子插入其中，对其进行压制和密封，然后用植物获得所得的颗粒，来种植植物种子的造粒方法 种子。 本发明通过防止种子除去水分的生理反应，可以在萌发后的植物生长中提供植物种子大的颗粒。 此外，本发明可以用于球茎植物，并且不必在土壤表面播种后种子上覆盖土壤。

    Touch panel and method for fabricating the same
    77.
    发明授权
    Touch panel and method for fabricating the same 有权
    触摸面板及其制造方法

    公开(公告)号：US09262018B2

    公开(公告)日：2016-02-16

    申请号：US13308282

    申请日：2011-11-30

    申请人： Seung-Hyun Kim ,  Hyung-Chul Kim ,  Tae-Yeon Yoo

    发明人： Seung-Hyun Kim ,  Hyung-Chul Kim ,  Tae-Yeon Yoo

    IPC分类号： G06F3/044

    CPC分类号： G06F3/044 ,  G06F2203/04103

    摘要： A touch panel is made by forming a routing and pad pattern group on a substrate to include first and second routing lines, first pad electrodes connected to the first routing line, and second pad electrodes connected to the second routing line, by using a first mask; forming a sensor electrode pattern group on the substrate having the routing and pad pattern group formed thereon to include first sensor electrodes formed in a first direction, second sensor electrodes formed in a second direction, and connection portions that each connects adjacent first sensor electrodes, by using a second mask; forming a first insulating layer to include contact holes to expose portions of the second sensor electrodes, respectively, by using a third mask; and forming bridges that each connects adjacent second sensor electrodes through the contact holes and a second insulating layer on the bridges, by using a fourth mask.

    摘要翻译： 通过在衬底上形成布线和焊盘图案组以包括第一和第二布线线，连接到第一布线线的第一焊盘电极和连接到第二布线线的第二焊盘电极，通过使用第一掩模 ; 在其上形成有路由和焊盘图案组的基板上形成传感器电极图案组，以包括沿第一方向形成的第一传感器电极，在第二方向上形成的第二传感器电极和连接相邻的第一传感器电极的连接部分， 使用第二个掩模; 形成第一绝缘层，以分别包括通过使用第三掩模来暴露第二传感器电极的部分的接触孔; 以及通过使用第四掩模形成每个通过接触孔连接邻近的第二传感器电极的桥和桥上的第二绝缘层。