公开(公告)号：US07378866B2

公开(公告)日：2008-05-27

申请号：US11942396

申请日：2007-11-19

Applicant: Fen Chen ,  Kai D Feng ,  Robert J Gautheir ,  Tom C Lee

Inventor： Fen Chen ,  Kai D Feng ,  Robert J Gautheir ,  Tom C Lee

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/018571

Abstract: A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

公开(公告)号：US08686508B2

公开(公告)日：2014-04-01

申请号：US12553523

申请日：2009-09-03

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert Robison

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Robert Robison

IPC: H01L23/62

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract translation: 为纳秒电脉冲退火工艺提供了结构和方法。 形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散，并在衬底上形成P +扩散。 P +扩散与N +扩散电接触。 该方法还包括在N +扩散和P +扩散之间形成器件。 退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

公开(公告)号：US20120181608A1

公开(公告)日：2012-07-19

申请号：US13005560

申请日：2011-01-13

Applicant: Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L29/0688 ,  H01L27/0266 ,  H01L29/0615 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

Abstract: A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.

Abstract translation: 一种形成半导体结构的方法，包括在半导体层的第一部分中形成沟道并且在半导体层的第二部分中形成掺杂的延伸区域，所述第二部分邻近第一侧的沟道并且邻接底部的绝缘体材料 。 半导体层的第一部分比半导体层的第二部分厚。

公开(公告)号：US07981732B2

公开(公告)日：2011-07-19

申请号：US12105366

申请日：2008-04-18

Applicant: Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

Inventor： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

IPC: H01L21/268

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.

Abstract translation: 激光熔丝编程方法。 激光熔丝具有包括具有在暴露于激光束之后改变其电阻的特性的材料的熔断体。 激光束被引导到熔丝链，激光束被控制，使得响应于激光束对熔丝链的冲击，熔丝链的电阻改变，但是熔丝链不会被吹掉。

公开(公告)号：US07892926B2

公开(公告)日：2011-02-22

申请号：US12508962

申请日：2009-07-24

Applicant: Karl W. Barth ,  Jeffrey P. Gambino ,  Tom C. Lee ,  Kevin S. Petrarca

Inventor： Karl W. Barth ,  Jeffrey P. Gambino ,  Tom C. Lee ,  Kevin S. Petrarca

IPC: H01L21/336

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.

Abstract translation: 形成可编程熔丝结构的方法包括在衬底中形成至少一个浅沟槽隔离（STI），在至少一个STI上形成e-熔丝，并在该电熔丝上沉积层间电介质（ILD）层。 另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到 在电子熔断器的部分上方提供气隙。

公开(公告)号：US20100290264A1

公开(公告)日：2010-11-18

申请号：US12842158

申请日：2010-07-23

Applicant: Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

IPC: G11C13/04 ,  G11C11/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

Abstract translation: 一个结构。 该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。 电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。 电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

公开(公告)号：US20090230555A1

公开(公告)日：2009-09-17

申请号：US12049698

申请日：2008-03-17

Applicant: Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

Inventor： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract translation: 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 一种金属层堆叠，包括从底部到顶部的低氧反应性金属层，底部过渡金属层，底部过渡金属氮化物层，铝 - 铜层，任选的顶部过渡金属层和顶部过渡层 金属氮化物层。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成，因此提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

公开(公告)号：US20090183131A1

公开(公告)日：2009-07-16

申请号：US12050990

申请日：2008-03-19

Applicant: Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

Inventor： Ronald J. Bolam ,  Tom C. Lee ,  Timothy D. Sullivan

IPC: G06F17/50

CPC classification number: H01L23/345 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

Abstract translation: 公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。 修理方案在每个设备上使用加热元件。 加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。 具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。 加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

公开(公告)号：US20080297188A1

公开(公告)日：2008-12-04

申请号：US11755827

申请日：2007-05-31

Applicant: Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

Inventor： Oliver Aubel ,  Tom C. Lee ,  Deborah M. Massey ,  Travis S. Merrill ,  Stanley W. Polchlopek ,  Alvin W. Strong ,  Timothy D. Sullivan

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/2875 ,  G01R31/2879

Abstract: Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.

Abstract translation: 公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。 该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

公开(公告)号：US20080231312A1

公开(公告)日：2008-09-25

申请号：US12154304

申请日：2008-05-22

Applicant: Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

Inventor： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Abstract translation: 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。