公开(公告)号：US07247891B2

公开(公告)日：2007-07-24

申请号：US10970026

申请日：2004-10-22

申请人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

发明人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

IPC分类号： H01L29/739

CPC分类号： H01L29/7787 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14656 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.

摘要翻译： 半导体器件具有第一氮化物半导体层，形成在第一氮化物半导体层上的第二氮化物半导体层，并具有在第一氮化物半导体层的上部产生二维电子气层的组成， 电极，其选择性地形成在第二氮化物半导体层上。 第二氮化物半导体层包括具有至少一个倾斜部分的接触区域，其底部或壁表面朝向第一氮化物半导体层的上表面倾斜并且限定凹陷的横截面构型。 电极形成在接触区域上。

公开(公告)号：US20060289894A1

公开(公告)日：2006-12-28

申请号：US11455631

申请日：2006-06-20

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L31/00

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电衬底上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，并由未掺杂的GaN和N型Al x Ga 1 -N构成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。

公开(公告)号：US20050093098A1

公开(公告)日：2005-05-05

申请号：US10971098

申请日：2004-10-25

申请人： Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

发明人： Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC分类号： C30B25/02 ,  C30B29/40 ,  H01L21/285 ,  H01L29/20 ,  H01L29/45 ,  H01L29/80 ,  H01L33/32 ,  H01L33/40 ,  C30B1/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/36 ,  H01L31/0304

CPC分类号： H01L21/28575 ,  C30B25/02 ,  C30B29/40 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/802 ,  H01L33/32 ,  H01L33/40

摘要： A semiconductor device of the present invention comprises a Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity and at least one ohmic electrode formed on the Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity. The ohmic electrode is formed of a conductive material containing a metal boride.

摘要翻译： 本发明的半导体器件包括具有n型导电性的氮化镓等的III-V族氮化物半导体层和形成在氮化镓等的III-V族氮化物半导体层上的至少一个欧姆电极， n型电导率。 欧姆电极由含有金属硼化物的导电材料形成。

公开(公告)号：US20050087763A1

公开(公告)日：2005-04-28

申请号：US10970026

申请日：2004-10-22

申请人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

发明人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

IPC分类号： H01L21/331 ,  H01L21/335 ,  H01L21/338 ,  H01L27/146 ,  H01L29/20 ,  H01L29/737 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328 ,  H01S5/042 ,  H01S5/323 ,  H01S5/343

CPC分类号： H01L29/7787 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14656 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.

摘要翻译： 半导体器件具有第一氮化物半导体层，形成在第一氮化物半导体层上的第二氮化物半导体层，并具有在第一氮化物半导体层的上部产生二维电子气层的组成， 电极，其选择性地形成在第二氮化物半导体层上。 第二氮化物半导体层包括具有至少一个倾斜部分的接触区域，其底部或壁表面朝向第一氮化物半导体层的上表面倾斜并且限定凹陷的横截面构型。 电极形成在接触区域上。

公开(公告)号：US06447838B1

公开(公告)日：2002-09-10

申请号：US08543827

申请日：1995-10-16

申请人： Masamichi Azuma ,  Eiji Fujii ,  Yasuhiro Uemoto ,  Shinichiro Hayashi ,  Toru Nasu ,  Yoshihiro Shimada ,  Akihiro Matsuda ,  Tatsuo Otsuki ,  Michael C. Scott ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

发明人： Masamichi Azuma ,  Eiji Fujii ,  Yasuhiro Uemoto ,  Shinichiro Hayashi ,  Toru Nasu ,  Yoshihiro Shimada ,  Akihiro Matsuda ,  Tatsuo Otsuki ,  Michael C. Scott ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

IPC分类号： B05D512

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/65 ,  Y10T29/42

摘要： A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

摘要翻译： 在基板上形成Ti / TiN粘合/阻挡层并退火。 退火步骤在取决于所述阻挡层的厚度的基本阻挡退火温度之上的100℃的良好形态范围内进行。 对于约3000的屏障厚度，对于约1000和约800℃的阻挡层厚度，基底阻挡退火温度为约700℃。 阻挡层厚度为800或更厚。 形成第一电极，随后是BST介电层和第二电极。 还公开了其中TiN阻挡层夹在两层铂之间的底部电极结构。 该工艺和结构也与其他电容器电介质（包括铁电锶钽酸锶）等产生良好的结果。

公开(公告)号：US06441420B1

公开(公告)日：2002-08-27

申请号：US09576971

申请日：2000-05-24

申请人： Yoshihisa Nagano ,  Yasuhiro Uemoto

发明人： Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC分类号： H01L2994

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

公开(公告)号：US06169304A

公开(公告)日：2001-01-02

申请号：US09071534

申请日：1998-05-04

申请人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

发明人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

摘要： A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

摘要翻译： 一种通过半导体衬底上的层间绝缘层形成电容器的半导体器件，其上形成集成电路。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

公开(公告)号：US5780351A

公开(公告)日：1998-07-14

申请号：US844108

申请日：1997-04-28

申请人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

发明人： Koji Arita ,  Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Toru Nasu ,  Akihiro Matsuda ,  Yoshihisa Nagano ,  Atsuo Inoue ,  Taketoshi Matsuura ,  Tatsuo Otsuki

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/20 ,  H01L21/00

CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75 ,  Y10S438/958

摘要： A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

摘要翻译： 一种半导体器件，其在形成集成电路的半导体衬底上通过层间绝缘层形成电容器。 该半导体装置具有含水量为0.5g / cm 3以下的层间绝缘层，其在一个方面覆盖电容器，并且具有氢含量为1021原子/ cm3以下的钝化层，其覆盖电容器的互连 在其他方面。 通过这样构成，可以防止导致铁电层或高介电层的电可靠性的电容器电介质的劣化。

公开(公告)号：US5661319A

公开(公告)日：1997-08-26

申请号：US681093

申请日：1996-07-22

申请人： Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Tooru Nasu ,  Akihiro Matsuda ,  Tatsuo Ootsuki

发明人： Eiji Fujii ,  Yasuhiro Shimada ,  Yasuhiro Uemoto ,  Tooru Nasu ,  Akihiro Matsuda ,  Tatsuo Ootsuki

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L29/92 ,  H01L29/94 ,  H01G7/06

CPC分类号： H01L29/94 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/1203 ,  H01L28/55 ,  H01L29/78654 ,  H01L28/75

摘要： This is a semiconductor device having an integrated circuit and a capacitor formed on a semiconductor substrate. The capacitor comprises a bottom electrode serving also as a part of a diffusion layer of the integrated circuit, a dielectric film being formed on the bottom electrode, and a top electrode of a conductive film being formed on the dielectric film. In particular, it is preferred to form the dielectric film in two layers of dielectric film, and compose the dielectric film contacting with the bottom electrode of a dielectric material in a composition possessing an excess of a metal element than the stoichiometric composition.

摘要翻译： 这是具有形成在半导体衬底上的集成电路和电容器的半导体器件。 电容器包括还用作集成电路的扩散层的一部分的底部电极，形成在底部电极上的电介质膜和形成在电介质膜上的导电膜的顶部电极。 特别地，优选将电介质膜形成为两层电介质膜，并且构成与具有比化学计量组成更多的金属元素的组成的与电介质材料的底电极接触的电介质膜。

公开(公告)号：US08593068B2

公开(公告)日：2013-11-26

申请号：US13032297

申请日：2011-02-22

申请人： Shingo Hashizume ,  Ayanori Ikoshi ,  Hiroto Yamagiwa ,  Yasuhiro Uemoto ,  Manabu Yanagihara

发明人： Shingo Hashizume ,  Ayanori Ikoshi ,  Hiroto Yamagiwa ,  Yasuhiro Uemoto ,  Manabu Yanagihara

IPC分类号： H05B39/02

CPC分类号： H01L29/808 ,  H01L29/2003 ,  H01L29/42316 ,  H03K17/12 ,  H03K2217/0009

摘要： A two-wire AC switch suppressing heat from a bidirectional switch element inside the switch is provided. The two-wire AC switch 100a connected between an AC power supply 101 and a load 102 includes: a bidirectional switch element 103 which flows passing current bi-directionally, selects whether to flow or block the current, is connected in series with the AC power supply 101 and the load 102 to form a closed-loop circuit, and is made of a group-III nitride semiconductor; a full-wave rectifier 104 performing full-wave rectification on power supplied from the AC power supply 101; a power supply circuit 105 smoothing a voltage after the full-wave rectification to generate DC power; a first gate drive circuit 107 and a second gate drive circuit 108 each outputting a control signal to the bidirectional switch element 103; and a control circuit 106 controlling the first and second gate drive circuits 107 and 108.

摘要翻译： 提供一种抑制来自开关内的双向开关元件的热量的二线交流开关。 连接在交流电源101和负载102之间的二线交流开关100a包括：双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103，其双向开关元件103， 电源101和负载102以形成闭环电路，并且由III族氮化物半导体制成; 全波整流器104对从AC电源101提供的电力进行全波整流; 电源电路105，对全波整流后的电压进行平滑化，生成直流电力; 每个向双向开关元件103输出控制信号的第一栅极驱动电路107和第二栅极驱动电路108; 以及控制电路106，其控制第一和第二栅极驱动电路107和108。