公开(公告)号：US09330745B2

公开(公告)日：2016-05-03

申请号：US14509756

申请日：2014-10-08

Applicant: Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

Inventor： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract translation: 磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。 第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。 固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。 磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。 还讨论了相关的操作方法。

公开(公告)号：US20160086565A1

公开(公告)日：2016-03-24

申请号：US14857926

申请日：2015-09-18

Applicant: Seong-Young RYU ,  Yong-Kyu LEE ,  Choong-Jae LEE

Inventor： Seong-Young RYU ,  Yong-Kyu LEE ,  Choong-Jae LEE

IPC: G09G5/00 ,  G06F3/041 ,  G06F1/32

CPC classification number: G09G5/003 ,  G06F1/3265 ,  G06F3/0412 ,  G06F3/0416 ,  G09G5/006 ,  G09G2330/021 ,  G09G2340/16 ,  G09G2360/18 ,  G09G2370/10 ,  Y02D10/153

Abstract: A display driving circuit includes a frame buffer that stores a plurality of pieces of line data, and a buffer controller. The buffer controller receives a data packet, and outputs first line data included in the data packet or second line data stored in the frame buffer as grayscale data based on flag information included in the data packet.

Abstract translation: 显示驱动电路包括存储多条线数据的帧缓冲器和缓冲器控制器。 缓冲器控制器接收数据包，并且基于包括在数据包中的标志信息，输出包含在数据包中的第一行数据或存储在帧缓冲器中的第二行数据作为灰度数据。

公开(公告)号：US09208874B2

公开(公告)日：2015-12-08

申请号：US14083470

申请日：2013-11-19

Applicant: Yong-Kyu Lee ,  Bo-Geun Kim

Inventor： Yong-Kyu Lee ,  Bo-Geun Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0085 ,  G11C2211/5622 ,  G11C2213/72

Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.

Abstract translation: 提供了用于驱动非易失性存储器件的方法。 该方法包括基于预定电流选择第一写入驱动器，对与第一写入驱动器相对应的电阻存储器单元执行第一编程操作，在第一程序操作中验证电阻性存储器单元是否已经通过或失败，以及关于故障位的排序信息 在第一程序操作中失败的存储器单元，基于分类的故障位存储器单元信息选择第二写驱动器，以及对与第二写驱动器相对应的电阻存储单元执行第二程序操作。

公开(公告)号：US08921816B2

公开(公告)日：2014-12-30

申请号：US13178762

申请日：2011-07-08

Applicant: Bo-Young Seo ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

Inventor： Bo-Young Seo ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

IPC: H01L29/02 ,  H01L27/24 ,  H01L27/102 ,  H01L45/00

CPC classification number: H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract translation: 提供一种半导体器件。 该半导体器件包括半导体衬底上的下部有源区。 提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。 提供了围绕下部有源区域的侧壁的下部隔离区域。 提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。 提供形成在下部有源区并延伸到上部有源区的第一杂质区。 提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。 还提供了制造该方法的方法。

公开(公告)号：US20140169068A1

公开(公告)日：2014-06-19

申请号：US14083470

申请日：2013-11-19

Applicant: YONG-KYU LEE ,  BO-GEUN KIM

Inventor： YONG-KYU LEE ,  BO-GEUN KIM

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0085 ,  G11C2211/5622 ,  G11C2213/72

Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.

Abstract translation: 提供了用于驱动非易失性存储器件的方法。 该方法包括基于预定电流选择第一写入驱动器，对与第一写入驱动器相对应的电阻存储器单元执行第一编程操作，在第一程序操作中验证电阻性存储器单元是否已经通过或失败，以及关于故障位的排序信息 在第一程序操作中失败的存储器单元，基于分类的故障位存储器单元信息选择第二写驱动器，以及对与第二写驱动器相对应的电阻存储单元执行第二程序操作。

公开(公告)号：US20120007212A1

公开(公告)日：2012-01-12

申请号：US13178762

申请日：2011-07-08

Applicant: Bo-Young SEO ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

Inventor： Bo-Young SEO ,  Byung-Suo Shim ,  Yong-Kyu Lee ,  Tea-Kwang Yu ,  Ji-Hoon Park

IPC: H01L29/06

CPC classification number: H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract translation: 提供一种半导体器件。 该半导体器件包括半导体衬底上的下部有源区。 提供从下部有源区域的顶表面突出并且具有比下部有源区域更窄的多个上部有源区域。 提供了围绕下部有源区域的侧壁的下部隔离区域。 提供了形成在下隔离区域上的上隔离区域，其围绕上活性区域的侧壁，并且具有比下隔离区域窄的宽度。 提供形成在下部有源区并延伸到上部有源区的第一杂质区。 提供形成在上部有源区并与第一杂质区一起构成二极管的第二杂质区。 还提供了制造该方法的方法。

公开(公告)号：US07745871B2

公开(公告)日：2010-06-29

申请号：US11871453

申请日：2007-10-12

Applicant: Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

Inventor： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

IPC: H01L29/78

CPC classification number: H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

Abstract translation: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

公开(公告)号：US20090065845A1

公开(公告)日：2009-03-12

申请号：US12230938

申请日：2008-09-08

Applicant: Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

Inventor： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L29/665 ,  H01L29/7833

Abstract: Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.

Abstract translation: 提供了嵌入式半导体器件和制造嵌入式半导体器件的方法。 在制造嵌入式半导体器件的方法中，可以在衬底的单元区域中形成至少一个单元栅极堆叠的层。 逻辑门结构可以形成在衬底的逻辑区域中。 可以在逻辑门结构附近形成第一源极/漏极区，并且可以在逻辑门结构和第一源极/漏极区上形成金属硅化物图案。 可以在至少一个单元栅极堆叠的层上形成至少一个硬掩模，并且可以形成阻挡图案以覆盖逻辑门结构和第一源极/漏极区域。 可以通过使用至少一个硬掩模作为蚀刻掩模来蚀刻至少一个单元栅极堆叠的层而在单元区域中形成至少一个单元栅极堆叠。 单元区域中的存储晶体管可以具有增加的积分度，并且逻辑区域中的逻辑晶体管可以具有增加的响应速度和降低的电阻。

公开(公告)号：US20080179692A1

公开(公告)日：2008-07-31

申请号：US12013618

申请日：2008-01-14

Applicant: Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

Inventor： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

IPC: H01L27/112 ,  H01L21/8234

CPC classification number: H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

Abstract translation: 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。

公开(公告)号：US07341912B2

公开(公告)日：2008-03-11

申请号：US11301854

申请日：2005-12-13

Applicant: Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

Inventor： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract translation: 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。