公开(公告)号：US09607705B1

公开(公告)日：2017-03-28

申请号：US14846549

申请日：2015-09-04

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

公开(公告)号：US20160267984A1

公开(公告)日：2016-09-15

申请号：US14657252

申请日：2015-03-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C16/30

CPC classification number: G11C16/08 ,  G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C16/0483

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

Abstract translation: 一些实施例包括具有存储器单元阵列的设备，至少部分地阵列下的存储器控​​制单元，与存储器控制单元进行数据通信的行解码器电路，以及与存储器控制单元进行数据通信的列解码器电路。 一些实施例包括具有存储器单元阵列的设备，行解码器电路和列解码器电路。 行和列解码器电路中的一个在至少部分地在存储器单元阵列之下延伸的单元内，另一个在位于存储器单元阵列的横向外部的单元内。

公开(公告)号：US09401188B2

公开(公告)日：2016-07-26

申请号：US14216528

申请日：2014-03-17

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14

CPC classification number: G11C7/22 ,  G11C5/143 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.

Abstract translation: 描述包括使能电路的设备和系统的示例。 可以使用两个电压源来操作设备的不同部分，包括外围电路和I / O电路。 当一个或多个器件的外围电路的电源被禁止时，该器件的I / O电路可能被禁止。 在一些示例中，可以通过消除或减少通过I / O电路的DC电流路径来部分地节省功率。

公开(公告)号：US20160188775A1

公开(公告)日：2016-06-30

申请号：US15061559

申请日：2016-03-04

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G11C7/1066 ,  G11C7/227 ,  G11C13/0021 ,  G11C29/025

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

公开(公告)号：US09343479B2

公开(公告)日：2016-05-17

申请号：US14615830

申请日：2015-02-06

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/115

CPC classification number: H01L27/108 ,  H01L21/74 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括装置和方法，包括具有交替电平的半导体材料和电介质材料的存储器阵列，其具有在交替电平上形成的存储器单元串。 一种这样的装置包括从衬底表面开始形成的存储器阵列。 外围电路形成在与存储器阵列相邻的升高部分上，并且具有与存储器阵列的最上表面基本共面的最上部分。 描述附加的装置和方法。

公开(公告)号：US20160133332A1

公开(公告)日：2016-05-12

申请号：US14997278

申请日：2016-01-15

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

Abstract translation: 提供了实施例，其包括在操作之前向存储器单元提供第一电压的方法，其中第一电压的大小约为5伏。 该方法还包括在操作期间向存储器单元提供第二电压，其中第二电压的幅度在大约1.0和1.5伏的范围内。 该方法还包括在提供第一电压和第二电压之后确定存储器单元的状态。

公开(公告)号：US09208891B2

公开(公告)日：2015-12-08

申请号：US14462078

申请日：2014-08-18

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/24 ,  G11C5/02 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括具有上弦和下弦的三维存储装置的装置和方法。 上部串可以包括第一串存储器单元和基本上平行并彼此相邻布置的第二存储单元串。 较低的串可以包括第三串存储器单元和基本上平行并彼此相邻布置的第四串存储单元。 串可以各自具有耦合到其上的单独的读出放大器。 第一和第三串以及第二和第四串可以被配置为在读取操作期间彼此串联耦合。 描述附加的装置和方法。

公开(公告)号：US09082485B2

公开(公告)日：2015-07-14

申请号：US14089337

申请日：2013-11-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/00 ,  G11C16/04 ,  G11C5/06 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C5/02

CPC classification number: G11C16/0483 ,  G11C5/025 ,  G11C5/06 ,  G11C16/107 ,  G11C2213/71 ,  H01L27/1052 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有位于器件的不同器件级别中的存储器单元，位于器件的衬底中的晶体管的至少一部分以及耦合到晶体管和存储器单元的数据线的器件和方法。 数据线可以位于晶体管和存储单元之间。 描述包括附加装置和方法的其它实施例。

公开(公告)号：US09064578B2

公开(公告)日：2015-06-23

申请号：US13718801

申请日：2012-12-18

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Satoru Tamada ,  Koichi Kawai ,  Tetsuji Manabe

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/06 ,  G11C7/18

CPC classification number: G11C8/12 ,  G11C7/00 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C2207/005 ,  G11C2207/2245

Abstract: Chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed.

Abstract translation: 可以访问存储器阵列中的存储器单元的块，然后禁止一个或多个块被访问。 在一种这样的装置中，阵列包括存储器单元的块和耦合到每个块的块选择器电路，以使得可以访问相应块中的存储器单元。

公开(公告)号：US09064577B2

公开(公告)日：2015-06-23

申请号：US13707067

申请日：2012-12-06

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  G11C16/16

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。