公开(公告)号：US5893952A

公开(公告)日：1999-04-13

申请号：US954791

申请日：1997-10-21

Applicant: Sheldon Aronowitz ,  Nicholas Eib ,  Jon S. Owyang

Inventor： Sheldon Aronowitz ,  Nicholas Eib ,  Jon S. Owyang

IPC: H01L21/20 ,  H01L21/00 ,  H01L21/268 ,  H01L21/285 ,  H01L21/316 ,  H01L21/324 ,  H01L21/66 ,  H01L23/34 ,  C23C16/00

CPC classification number: B24B37/013 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/31662 ,  H01L21/324 ,  H01L21/67115 ,  H01L22/26 ,  H01L23/34 ,  H01L2924/0002 ,  Y10S148/093 ,  Y10S148/094 ,  Y10S148/095

Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.

Abstract translation: 通过扫描与晶片表面接触的二氧化硅膜的激光束来进行半导体晶片的快速热处理。 二氧化硅膜吸收激光束的能量并将能量转换成热量。 热又转移到晶片上。 可以获得温度反馈以增加跨晶片温度的控制和均匀性。

公开(公告)号：US5877530A

公开(公告)日：1999-03-02

申请号：US690592

申请日：1996-07-31

Applicant: Sheldon Aronowitz ,  Laique Khan ,  Philippe Schoenborn

Inventor： Sheldon Aronowitz ,  Laique Khan ,  Philippe Schoenborn

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/7833

Abstract: A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation. Since the doped region beneath the oxide spacers includes a gradient doped profile region, with the lightest level of dopant adjacent the channel region (since more of the tapered gate electrode acted as a mask for the initial implantation), the overall dosage level used in the first implantation step to form the gradient doped profile region may be higher than the dosage level conventionally used to form a conventional LDD region. The resistance of the path between the heavily doped drain contact region and the channel region, which includes the gradient doped profile region, is therefore lower than the resistance of a conventional LDD region.

Abstract translation: 公开了一种新颖的集成电路结构及其制造方法，其中在包括MOS器件的衬底中的重掺杂漏极区域和沟道区域之间的半导体衬底中提供锥形或梯度掺杂型态区域。 在本发明的方法中，在第一掺杂步骤期间，以比通常用于形成常规LDD区域的剂量水平，使用类似倒梯形的入口或锥形栅极电极作为掩模。 该掺杂步骤形成具有掺杂剂梯度的掺杂区域，其随着与沟道区域的距离而逐渐增加剂量水平。 然后可以在栅电极的侧壁上形成常规的氧化物间隔物，接着是常规的高电平掺杂，以在氧化物间隔物和场氧化物隔离之间的衬底的未屏蔽部分中形成重掺杂的源极和漏极区。 由于氧化物间隔物下面的掺杂区域包括梯度掺杂的轮廓区域，其中掺杂剂的最弱级别与沟道区域相邻（因为更多的锥形栅极电极用作初始注入的掩模），所以在 形成梯度掺杂轮廓区域的第一注入步骤可以高于常规用于形成常规LDD区域的剂量水平。 因此，重掺杂漏极接触区域和沟道区域（包括梯度掺杂分布区域）之间的路径电阻比常规LDD区域的电阻低。

公开(公告)号：US5837598A

公开(公告)日：1998-11-17

申请号：US816254

申请日：1997-03-13

Applicant: Sheldon Aronowitz ,  Valeriy Sukharev ,  Jon Owyang ,  John Haywood

Inventor： Sheldon Aronowitz ,  Valeriy Sukharev ,  Jon Owyang ,  John Haywood

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L21/425

CPC classification number: H01L21/28035 ,  H01L29/4916

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e., by implantation followed by furnace annealing, to diffuse and activate the dopant in the polysilicon gate electrode without, however, resulting in penetration of the dopant through the barrier layer into the underlying gate oxide layer or the semiconductor substrate.

Abstract translation: 在半导体衬底上形成集成电路结构的一部分的MOS器件的均匀掺杂的多晶硅栅电极通过首先沉积非常薄的非晶或多晶硅层（例如约2nm至约10nm）而形成， 栅氧化层。 然后将硅层的薄层暴露于由N 2形成的氮等离子体，其功率水平足以破坏硅薄层中的硅 - 硅键，但不足以引起硅的溅射以引起硅的阻挡层 并在氮化硅表面形成氮。 然后将另外的硅，例如多晶硅沉积在阻挡层上至多晶硅栅电极的期望厚度。 然后通常掺杂栅电极，即通过注入然后进行炉退火，以扩散和激活多晶硅栅极电极中的掺杂剂，而不会导致掺杂剂穿过阻挡层进入下面的栅极氧化物层或 半导体衬底。

公开(公告)号：US5585286A

公开(公告)日：1996-12-17

申请号：US521795

申请日：1995-08-31

Applicant: Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

Inventor： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506

Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Abstract translation: 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入硼的后续剂量 掺杂剂，但不超过与硅衬底中注入约3×1013氩离子/ cm 2相当的量，由此抑制随后注入的硼掺杂剂的通道化和扩散，而不会使半导体衬底非晶化。

公开(公告)号：US5538907A

公开(公告)日：1996-07-23

申请号：US241358

申请日：1994-05-11

Applicant: Sheldon Aronowitz ,  Rosario Consiglio ,  Abraham Yee

Inventor： Sheldon Aronowitz ,  Rosario Consiglio ,  Abraham Yee

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L27/092 ,  H01L21/265

CPC classification number: H01L27/0255 ,  H01L27/0251 ,  H01L27/0259 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0716 ,  H01L27/092

Abstract: A CMOS integrate circuit has improved protection to damage from electrostatic discharge (ESD) events because the circuit is formed with a virtual lateral bipolar transistor submerged in the morphology of the integrated circuit beneath an active circuit element of the circuit, and being formed by impurity atoms implanted into the substrate structure as ions which disperse laterally to form a dispersed charge permeation zone through which surge current from an ESD is conducted safely at a current level sufficiently low that the substrate material of the integrated circuit is not damaged. The integrated circuit may be formed with an intrinsic zener diode having a reverse bias breakdown voltage high enough to not interfere with the normal operation of the integrated circuit, and low enough to allow surge current from an ESD event to safely flow to ground potential.

Abstract translation: CMOS集成电路已经改善了对静电放电（ESD）事件的损害的保护，因为电路形成有浸没在电路的有源电路元件下面的集成电路形态的虚拟横向双极晶体管，并由杂质原子 以横向分散形成分散的电荷渗透区域的离子注入到衬底结构中，通过该区域，来自ESD的浪涌电流以足够低的电流水平安全地传导，使得集成电路的衬底材料不被损坏。 该集成电路可以由具有足够高的反偏压击穿电压的本征齐纳二极管形成，以不干扰集成电路的正常工作，并且足够低以允许来自ESD事件的浪涌电流安全地流向地电势。

公开(公告)号：US5468974A

公开(公告)日：1995-11-21

申请号：US249867

申请日：1994-05-26

Applicant: Sheldon Aronowitz ,  Yen-Hui J. Ku ,  Yu-Lam Ho

Inventor： Sheldon Aronowitz ,  Yen-Hui J. Ku ,  Yu-Lam Ho

IPC: H01L21/265 ,  H01L29/32 ,  H01L29/04

CPC classification number: H01L21/26506 ,  H01L29/32 ,  Y10S257/905 ,  Y10S438/934

Abstract: Dopant distribution and activation in polysilicon is controlled by implanting electrically neutral atomic species which accumulate along polysilicon grain boundaries. Exemplary atomic species include noble gases and Group IV elements other than silicon.

Abstract translation: 多晶硅中的掺杂分布和激活通过注入沿着多晶硅晶界积累的电中性原子物种来控制。 示例性的原子物质包括惰性气体和除了硅之外的第IV族元素。

公开(公告)号：US5292402A

公开(公告)日：1994-03-08

申请号：US910951

申请日：1992-07-09

Applicant: Norman E. Abt ,  Sheldon Aronowitz

Inventor： Norman E. Abt ,  Sheldon Aronowitz

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/00

CPC classification number: H01L21/31111 ,  H01L21/3081 ,  Y10S148/106

Abstract: Materials of the lead perovskite family PbZr.sub.x Ti.sub.1-x O.sub.3 have been discovered to be excellent masking materials in the etching of silicon and silicon-containing materials with chlorine and fluorine -based plasmas. Generally, materials of the lead perovskite family are suitable masking materials for any material that is etched in chlorine and fluorine -based plasmas.

Abstract translation: 已经发现铅钙钛矿族PbZrxTi1-xO3的材料在用氯和氟基等离子体蚀刻硅和含硅材料时是优异的掩蔽材料。 一般来说，铅钙钛矿族的材料对于在氯和氟基等离子体中蚀刻的任何材料都是合适的掩蔽材料。

公开(公告)号：US5137838A

公开(公告)日：1992-08-11

申请号：US710646

申请日：1991-06-05

Applicant: Amolak Ramde ,  Sheldon Aronowitz

Inventor： Amolak Ramde ,  Sheldon Aronowitz

IPC: H01L21/22 ,  H01L21/265 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8228 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L21/74 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/761 ,  H01L21/82285 ,  Y10S148/058

Abstract: A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.

公开(公告)号：US4746964A

公开(公告)日：1988-05-24

申请号：US901502

申请日：1986-08-28

Applicant: Sheldon Aronowitz

Inventor： Sheldon Aronowitz

IPC: H01L21/22 ,  H01L21/265 ,  H01L29/167 ,  H01L29/78 ,  H01L29/36

CPC classification number: H01L21/2652 ,  H01L21/22

Abstract: One p-type dopant is implanted into a substrate to modify the diffusion characteristics of another p-type dopant implanted into the substrate. As an example, gallium is diffused into a p-type region along with boron to confine the diffusion of the boron, and thereby produce smaller device regions in silicon. Along with the confined volume, the resulting regions exhibit electrical activity that is greater than the simple additive behavior of boron and gallium acting alone.

Abstract translation: 将一种p型掺杂剂注入到衬底中以改变注入到衬底中的另一种p型掺杂剂的扩散特性。 作为示例，镓与硼一起扩散到p型区域中以限制硼的扩散，从而在硅中产生较小的器件区域。 随着限制体积，所得区域表现出大于单独作用的硼和镓的简单添加剂行为的电活动。

公开(公告)号：US4689667A

公开(公告)日：1987-08-25

申请号：US743556

申请日：1985-06-11

Applicant: Sheldon Aronowitz

Inventor： Sheldon Aronowitz

IPC: H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L29/00 ,  H01L21/04

CPC classification number: H01L21/324 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/2652

Abstract: A method for preparing semiconductor components having a structure with sharply defined spatial distributions of dopant atoms with control over the degree of electrical activation of the dopant atoms. Control of spatial distribution and the degree of electrical activation of dopant atoms is achieved by implantation of dopant atoms along with rare gas atoms and another type of dopant atom within substantially the same preselected depth boundaries of a silicon or germanium substrate.

Abstract translation: 一种制备半导体器件的方法，该半导体器件具有具有尖锐定义的掺杂剂原子的空间分布的结构，可控制掺杂剂原子的电激活程度。 掺杂剂原子的空间分布和电激活程度的控制是通过将掺杂剂原子与稀有气体原子以及另一种类型的掺杂剂原子在硅或锗衬底的大致相同的预选深度边界内进行注入来实现的。