公开(公告)号：US09530689B2

公开(公告)日：2016-12-27

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针脚。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US09520395B2

公开(公告)日：2016-12-13

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09502528B2

公开(公告)日：2016-11-22

申请号：US14469014

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Mark A. Zaleski ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6653

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A first block mask is formed over a portion of the semiconductor structure. This first block mask covers at least a portion of at least one source/drain (s/d) contact location. An s/d capping layer is formed over the s/d contact locations that are not covered by the first block mask. This s/d capping layer is comprised of a first capping substance. Then, a second block mask is formed over the semiconductor structure. This second block mask exposes at least one gate location. A gate capping layer, which comprises a second capping substance, is removed from the exposed gate location(s). Then a metal contact layer is deposited, which forms a contact to both the s/d contact location(s) and the gate contact location(s).

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成第一块掩模。 该第一块掩模覆盖至少一个源/漏（s / d）接触位置的至少一部分。 在未被第一块掩模覆盖的s / d接触位置上形成s / d覆盖层。 该s / d封盖层由第一封盖物质构成。 然后，在半导体结构上形成第二块掩模。 该第二块掩模暴露至少一个门位置。 包括第二封盖物质的栅极覆盖层从暴露的栅极位置移除。 然后沉积金属接触层，其形成与s / d接触位置和栅极接触位置的接触。

公开(公告)号：US20160268171A1

公开(公告)日：2016-09-15

申请号：US14644269

申请日：2015-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin. The fin spacer has an upper surface. The at least one fin is recessed to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer. A first epitaxial material is formed on the recessed fin. A lateral extension of the first epitaxial material is constrained by the fin spacer. A cap layer is formed on the first epitaxial material. The fin spacer is removed. The cap layer protects the first epitaxial material during the removal of the fin spacer.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 翅片间隔件形成在至少一个翅片的至少第一部分上。 翅片间隔件具有上表面。 所述至少一个翅片是凹入的，从而限定具有凹陷的上表面的凹陷翅片，所述凹陷的翅片在所述翅片间隔件的上表面下方。 第一外延材料形成在凹形鳍上。 第一外延材料的横向延伸受到翅片间隔件约束。 在第一外延材料上形成盖层。 拆下翅片垫片。 盖层在去除鳍片间隔件期间保护第一外延材料。

公开(公告)号：US09406775B1

公开(公告)日：2016-08-02

申请号：US14696684

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Youngtag Woo

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L27/11 ,  H01L21/768

CPC classification number: H01L29/66515 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.

Abstract translation: 公开了用于形成非常接近栅极接触的自对准栅极切割和所得到的器件的方法。 实施例包括：提供具有硅散热片的衬底和金属栅极，其中氮化物帽垂直于翅片和鳍上，源极/漏极区域各自具有氧化物盖，位于栅极的相对侧上的鳍片上; 形成彼此分离的平行介质线，垂直于栅极和栅极上方; 在所述平行介质线上形成光致抗蚀剂，在所述光致抗蚀剂中形成在两个翅片之间暴露氮化物盖的开口; 去除暴露的氮化物盖，暴露下面的金属栅极; 去除暴露的金属栅极和其余的光致抗蚀剂; 在平行介质线之间形成低k介质线; 去除平行介电线路的部分; 在低k介质线之间形成垂直互连; 去除形成沟槽的平行介质线的剩余部分; 并用金属填充沟槽。

公开(公告)号：US09390979B2

公开(公告)日：2016-07-12

申请号：US14482529

申请日：2014-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Huy M. Cao ,  Jing Wan

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823437 ,  H01L27/088

Abstract: An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

Abstract translation: 提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。 在半导体结构的一部分上形成一组掩模。 这组掩模中的每个掩模覆盖至少一个源/漏（s / d）接触位置。 从半导体结构的未被该组掩模覆盖的其余部分去除氧化物层。 然后在除去氧化物层的剩余部分中形成相对掩模填充层。 然后从半导体结构的其余部分去除氧化物层，即，先前被该组掩模和触点覆盖的部分形成在通过去除其余部分形成的凹部中的至少s / d接触位置 氧化层。

公开(公告)号：US20160172493A1

公开(公告)日：2016-06-16

申请号：US15051734

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L27/092 ,  H01L29/08 ,  H01L29/24 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：在PFET区域和NFET区域中提供具有鳍状结构的鳍状结构的源极/漏极区域。 该方法包括在PFET区域中的源/漏区上选择性地形成接触电阻调制材料。 此外，该方法包括沉积覆盖PFET区域和NFET区域中的源极/漏极区域的带边功函数金属。

公开(公告)号：US20160141206A1

公开(公告)日：2016-05-19

申请号：US14543992

申请日：2014-11-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy C. Wei ,  Sudharshanan Raghunthathan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.

Abstract translation: 一种方法包括形成具有嵌入其中的至少一个导电特征的第一电介质层。 形成嵌入在设置在第一电介质层上方的第二电介质层中的第一多个导电线。 多个导线中的第一导线接触导电特征。 使用第一蚀刻掩模蚀刻第一导电线以在第一导电线中限定导电通路部分和凹陷线部分。 形成嵌入在第二电介质层上方的第三电介质层中的第二多个导电线。 第二多个导电线中的第二导线接触导电通路部分，第三电介质层直接接触第二电介质层。

公开(公告)号：US09306019B2

公开(公告)日：2016-04-05

申请号：US14457934

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jing Wan ,  Guillaume Bouche ,  Andy Wei ,  Shao Ming Koh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract translation: 提供了集成电路及其制造方法。 一种集成电路的制造方法，其特征在于，形成覆盖基板的分层散热片，其中层状散热片包括SiGe层和Si层。 SiGe层和Si层沿着层状翅片的高度交替。 形成覆盖基板和分层翅片的虚拟栅极以及与层状翅片接触形成的源极和漏极区域。 去除伪栅极以暴露SiGe层和Si层，并且去除Si层以产生SiGe纳米线。 形成在源极和漏极之间封装SiGe纳米线的高K电介质层，并且形成替代金属栅极，使得替代金属栅极包围源极和漏极之间的高K电介质层和SiGe纳米线。

公开(公告)号：US20150372115A1

公开(公告)日：2015-12-24

申请号：US14308138

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/6653 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract translation: 形成纳米线器件的方法包括图案化多个半导体材料层，使得每个层具有第一和第二暴露的端表面。 该方法还包括在半导体材料层的第一和第二暴露的端表面中形成掺杂的延伸区域。 该方法还包括：在形成掺杂的延伸区域之后，在器件的源极和漏极区域中形成外延半导体材料。