公开(公告)号：US20150214116A1

公开(公告)日：2015-07-30

申请号：US14165107

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/8238 ,  H01L21/266 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract translation: 提供一种形成半导体器件的方法，包括以下步骤：形成第一和第二PMOS晶体管器件，其中第一PMOS晶体管器件为低标准或高电压阈值晶体管器件，而第二PMOS晶体管器件为超高电压阈值晶体管器件 并且其中形成所述第一PMOS晶体管器件包括注入掺杂剂以形成所述第一PMOS晶体管器件的源极和漏极结，并且在注入所述掺杂剂之后执行所述第一PMOS晶体管器件的热退火，以及形成所述第二PMOS晶体管器件包括注入掺杂剂 以在第一PMOS晶体管器件进行热退火之后形成第二PMOS晶体管器件的源极和漏极结。

公开(公告)号：US20150200140A1

公开(公告)日：2015-07-16

申请号：US14153521

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Alexander Ebermann ,  Carsten Grass ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/28 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/0275 ,  H01L21/28123 ,  H01L21/28176 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823437 ,  H01L21/845

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Abstract translation: 一种用于制造集成电路的方法包括：提供具有覆盖在半导体衬底上的衬垫层的半导体衬底和覆盖衬垫层的光致抗蚀剂层，将光致抗蚀剂层暴露于分裂激光束以在光刻胶中形成多个平行的线性空隙区域 并且在所述多个平行线性空隙区域下方蚀刻所述衬垫层和所述半导体衬底，以形成多个延伸的平行线性空隙区域。 该方法还包括在半导体衬底上沉积第一介电材料，在半导体衬底上图案化光致抗蚀剂材料以覆盖半导体衬底的一部分，以及蚀刻衬垫层，第一电介质材料和半导体衬底的部分。 此外，该方法包括将第二电介质材料沉积到第二空隙区域中。

公开(公告)号：US09076815B2

公开(公告)日：2015-07-07

申请号：US13907362

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/266 ,  H01L21/8238

CPC classification number: H01L29/6653 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract translation: 制造晶体管时的已知问题是由间隔物不期望地引入晶体管沟道区域的应力。 为了解决这个问题，本发明提出了一种旨在缓和间隔物材料的应力的离子注入。 在间隔件已经完全形成之后进行松弛植入。 松弛植入可以在硅化处理之后或在源极和漏极区域中的注入步骤之后进行激活退火并且在进行硅化处理之前进行。

公开(公告)号：US09054207B2

公开(公告)日：2015-06-09

申请号：US13937600

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Sven Beyer ,  Uwe Griebenow ,  Jan Hoentschel

IPC: H01L29/788 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L29/788 ,  G11C16/0425 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Abstract translation: 可以在自对准电荷存储区域的基础上提供用于半导体器件中的闪存区域的存储晶体管。 为此，可以在一些说明性实施例中提供浮动间隔元件，而在其他情况下，在替换栅极方法期间，电荷存储区域可以以自对准方式有效地嵌入电极材料中。 因此，可以不再需要用于图案化电荷存储区域的附加复杂光刻工艺，可以实现增强的位密度。

公开(公告)号：US09029214B2

公开(公告)日：2015-05-12

申请号：US13740974

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ran Yan

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/823443 ,  H01L21/823468 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure. The method further includes depositing a non-conformal spacer material around the gate structure. A protection mask is formed over the non-conformal spacer material. The method etches the non-conformal spacer material and protection mask to form a salicidation spacer. Further, a self-aligned silicide contact is formed adjacent the salicidation spacer.

Abstract translation: 本文提供用于制造集成电路的集成电路和方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底上形成栅极结构。 该方法还包括在栅极结构周围沉积非共形间隔物材料。 在非保形间隔物材料上形成保护罩。 该方法蚀刻非共形间隔物材料和保护掩模以形成防腐隔离物。 此外，邻近该盐化隔离层形成自对准的硅化物接触。

公开(公告)号：US20150102426A1

公开(公告)日：2015-04-16

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US09006045B2

公开(公告)日：2015-04-14

申请号：US13792950

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract translation: 半导体结构包括衬底和晶体管。 晶体管包括设置在衬底上方的升高的源极区域和升高的漏极区域，一个或多个细长半导体管线，栅极电极和栅极绝缘层。 所述一个或多个细长半导体线连接在所述升高的源极区域和所述隆起的漏极区域之间，其中所述一个或多个细长半导体线路中的每一个的纵向方向基本上沿着垂直于所述衬底的厚度方向的水平方向延伸 。 每个细长半导体线包括沟道区。 栅电极围绕一个或多个细长半导体线路的每个沟道区域延伸。 栅极绝缘层设置在一个或多个细长半导体线路和栅电极中的每一个之间。

公开(公告)号：US20150021703A1

公开(公告)日：2015-01-22

申请号：US13943229

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/78

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract translation: 在各个方面，提供了形成半导体器件和半导体器件的方法。 在本文的一些说明性实施例中，硅/锗层设置在半导体衬底上。 在硅/锗层上形成至少一个绝缘材料层。 在进行热退火处理之后，在随后的处理顺序中除去至少一个绝缘材料层，使得硅/锗层至少部分暴露。 在随后施加的另外的处理顺序中，在暴露的硅/锗层上形成栅电极。

公开(公告)号：US08871586B2

公开(公告)日：2014-10-28

申请号：US13654849

申请日：2012-10-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski ,  Rolf Stephan

IPC: H01L21/8234

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  Y02P80/30

Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

Abstract translation: 在一个示例中，该方法包括在半导体衬底中形成多个隔离结构，其限定第一和第二有源区，其中将分别形成第一和第二晶体管器件，在衬底的表面上形成硬掩模层， 第一和第二有源区，其中所述硬掩模层包括碳，氟，氙或锗离子中的至少一种，执行第一蚀刻工艺以去除所述硬掩模层的一部分并暴露所述第一和第二有源区中的一个的表面 活性区域，在进行第一蚀刻工艺之后，在通过第一蚀刻工艺曝光的有源区的表面上形成沟道半导体材料，并且在形成沟道半导体材料之后，执行第二蚀刻工艺以除去 硬掩模层，其在第一蚀刻工艺期间未被除去。

公开(公告)号：US08835936B2

公开(公告)日：2014-09-16

申请号：US13678124

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/2257 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.

Abstract translation: 一种方法包括提供包括衬底，在衬底上的电绝缘层和电绝缘层上的半导体特征的半导体结构。 在半导体特征上形成栅极结构。 原位掺杂的半导体材料沉积在与栅极结构相邻的半导体器件的部分上。 掺杂剂从原位掺杂的半导体材料扩散到与栅极结构相邻的半导体器件的部分，掺杂剂扩散到半导体器件的与栅极结构相邻的部分，形成半导体器件中的掺杂源极和漏极区。