公开(公告)号：US10032910B2

公开(公告)日：2018-07-24

申请号：US14695411

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3115 ,  H01L29/165

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

公开(公告)号：US10008576B2

公开(公告)日：2018-06-26

申请号：US15490180

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Xusheng Wu

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/4983 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/786 ,  H01L29/78654

Abstract: A method of controlling the facet height of raised source/drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source/drain structures on the SOI, each of the faceted source/drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

公开(公告)号：US09964605B2

公开(公告)日：2018-05-08

申请号：US15190323

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Xusheng Wu

IPC: H01L29/66 ,  G01R33/06 ,  H01L29/06 ,  H01L29/78 ,  H01L29/82

CPC classification number: G01R33/066 ,  G01R33/0058 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/82

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.

公开(公告)号：US09842913B1

公开(公告)日：2017-12-12

申请号：US15157868

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/22 ,  H01L21/225 ,  H01L21/311 ,  H01L29/207

CPC classification number: H01L29/66795 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/31144 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US09761691B2

公开(公告)日：2017-09-12

申请号：US14560054

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dong-Woon Shin ,  Min-Hwa Chi ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming sidewall spacer structures laterally adjacent to a dummy gate structure that overlies a semiconductor substrate. Additional sidewall spacer structures are formed laterally adjacent to the sidewall spacer structures and under lower portions of the sidewall spacer structures. The dummy gate structure is replaced with a replacement gate structure.

公开(公告)号：US09761491B1

公开(公告)日：2017-09-12

申请号：US15370404

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Xusheng Wu ,  John H. Zhang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/78642 ,  Y02E10/50

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a self-aligned deep contact for a vertical field effect transistor (VFET) and methods of manufacture. The structure includes a plurality of fin structures, a first contact landing on a substrate material between a first set of fin structures of the plurality of fin structures, sidewalls of the first contact being in direct contact with an insulator material of the first set of the fin structures, and a second contact landing on a work function material between a second set of fin structures of the plurality of fin structures, sidewalls of the second contact being in direct contact with the insulator material of the second set of the fin structures.

公开(公告)号：US09721949B1

公开(公告)日：2017-08-01

申请号：US15010189

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Qizhi Liu ,  David Harame ,  Renata Camillo-Castillo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/324 ,  H01L21/823821 ,  H01L21/823892

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

公开(公告)号：US09647073B2

公开(公告)日：2017-05-09

申请号：US14526831

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu ,  Min-hwa Chi

IPC: H01L21/02 ,  H01L33/00 ,  H01L31/00 ,  H01L29/165 ,  H01L29/78 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US09583625B2

公开(公告)日：2017-02-28

申请号：US14523548

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xusheng Wu ,  Min-hwa Chi ,  Edmund Kenneth Banghart

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

Abstract translation: 提供一种形成具有低掺杂和高掺杂有源部分的FinFET鳍片的方法和/或具有用于Vt调谐和多Vt方案的锥形侧壁的FinFET鳍片以及所得到的器件。 实施例包括形成Si翅片，所述Si翅片具有顶部活性部分和底部活性部分; 在Si翅片的顶表面上形成硬掩模; 在所述Si翅片的相对侧上形成氧化物层; 将掺杂剂注入到Si鳍中; 凹陷氧化物层以露出Si鳍的有效顶部; 蚀刻Si翅片的顶部活性部分以形成垂直侧壁; 形成覆盖每个垂直侧壁的氮化物间隔物; 凹陷凹陷的氧化物层以露出Si鳍的活性底部; 并使Si翅片的活性底部部分变细。

公开(公告)号：US20160315172A1

公开(公告)日：2016-10-27

申请号：US14695411

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

Abstract translation: Fin场效应晶体管（FinFET）器件及其形成方法在此提供。 在一个实施例中，FinFET器件包括具有平行关系设置的多个鳍片的半导体衬底。 第一绝缘体层覆盖在半导体衬底上，鳍片延伸穿过第一绝缘体层并突出超过第一绝缘体层以提供暴露的鳍部分。 栅电极结构覆盖在暴露的鳍部上，并通过栅极绝缘层与散热片电绝缘。 外延生长的源极区域和漏极区域邻近栅电极结构设置。 外延生长的源极区域和漏极区域沿着垂直于鳍片的长度的横向方向具有不对称轮廓。