公开(公告)号：US20130273669A1

公开(公告)日：2013-10-17

申请号：US13698283

申请日：2012-06-12

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： H01L21/306

CPC分类号： H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

摘要翻译： 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二介电隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化方法的均匀性的方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US20130213434A1

公开(公告)日：2013-08-22

申请号：US13497768

申请日：2011-11-28

申请人： Guilei Wang ,  Junfeng Li ,  Chao Zhao

发明人： Guilei Wang ,  Junfeng Li ,  Chao Zhao

IPC分类号： H01L21/02

CPC分类号： H01L21/02 ,  C23C16/308 ,  C23C16/345 ,  C23C16/402 ,  C23C16/4404 ,  C23C16/505 ,  C23C16/56 ,  H01L21/76837

摘要： A method for eliminating contact bridge in a contact hole process is disclosed, wherein a cleaning menu comprising a multi-step adaptive protective thin film deposition process is provided, so that a stack adaptive protective thin film is formed on the sidewall of the chamber of the HDP CVD equipment. The stack adaptive protective thin film has good adhesivity, compactness and uniformity to protect the sidewall of the chamber of the HDP CVD equipment from being damaged by the plasma, and avoid the generation of defect particles, thereby improving the HDP CVD technical yield and eliminating the contact bridge phenomenon in the contact hole process.

摘要翻译： 公开了一种用于消除接触孔工艺中的接触桥的方法，其中提供了包括多步自适应保护薄膜沉积工艺的清洁菜单，使得堆叠自适应保护薄膜形成在腔室的侧壁上 HDP CVD设备。 叠层自适应保护薄膜具有良好的粘合性，紧凑性和均匀性，以保护HDP CVD设备室的侧壁不被等离子体损坏，并避免产生缺陷颗粒，从而提高HDP CVD技术产量并消除 接触孔过程中的接触桥现象。

公开(公告)号：US20120267706A1

公开(公告)日：2012-10-25

申请号：US13379373

申请日：2011-04-22

申请人： Jun Luo ,  Chao Zhao

发明人： Jun Luo ,  Chao Zhao

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66606 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention discloses a novel MOSFET device and its implementation method, the device comprising: a substrate; a gate stack structure, on either side of which is eliminated a conventional isolation spacer; source/drain regions located in the substrate on opposite sides of the gate stack structure; epitaxially grown metal silicide located on the source/drain regions; characterized in that, the epitaxially grown metal silicide is in direct contact with a channel region controlled by the gate stack structure, thereby eliminating the high resistance region below the conventional isolation spacer. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

摘要翻译： 本发明公开了一种新颖的MOSFET器件及其实现方法，该器件包括：衬底; 栅极堆叠结构，其任一侧消除了常规隔离间隔物; 源极/漏极区域位于栅极堆叠结构的相对侧上的衬底中; 位于源/漏区上的外延生长金属硅化物; 其特征在于，外延生长的金属硅化物与由栅极堆叠结构控制的沟道区域直接接触，从而消除了传统隔离间隔物下面的高电阻区域。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US20120244784A1

公开(公告)日：2012-09-27

申请号：US13142714

申请日：2011-04-11

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： B24B53/017 ,  B24B1/00

CPC分类号： B24B37/015 ,  B24B37/20 ,  B24B53/017 ,  Y02P80/30

摘要： A chemical-mechanical polishing tool and a method for preheating the same are disclosed. The chemical-mechanical polishing tool includes: a polishing pad, a deionized water supply channel, a polishing slurry supply channel and a polishing pad conditioner; and the chemical-mechanical polishing tool further includes: a heating apparatus, adapted to heat DI water fed to the DI water supply channel; a temperature sensor, arranged close to the polishing pad to measure a temperature of the polishing pad; and a preheating control system, connected to the temperature sensor, and adapted to control the DI water supply channel to spray the heated DI water to the polishing pad, and when the temperature measured by the temperature sensor is equal to or higher than a predetermined temperature, to close the DI water supply channel, control the polishing slurry supply channel to spray polishing slurry to the polishing pad, and startup the polishing pad conditioner to dress the polishing pad. The invention can reduce the consumption of polishing consumables by the chemical-mechanical polishing tool during preheating, thereby reducing production cost.

摘要翻译： 公开了一种化学机械抛光工具及其预热方法。 化学机械抛光工具包括：抛光垫，去离子水供应通道，抛光浆料供应通道和抛光垫调节剂; 并且所述化学机械抛光工具还包括：加热设备，其适于加热供给到所述DI供水通道的去离子水; 温度传感器，布置在抛光垫附近以测量抛光垫的温度; 以及预热控制系统，其连接到所述温度传感器，并且适于控制所述DI供水通道将所述加热的去离子水喷射到所述抛光垫，并且当所述温度传感器测量的温度等于或高于预定温度 关闭DI供水通道，控制抛光浆料供应通道将抛光浆料抛光到抛光垫上，并启动抛光垫调节剂来修整抛光垫。 本发明可以通过化学机械抛光工具在预热期间减少抛光耗材的消耗，从而降低生产成本。

公开(公告)号：US07183604B2

公开(公告)日：2007-02-27

申请号：US10459360

申请日：2003-06-10

申请人： Eduard Cartier ,  Jerry Chen ,  Chao Zhao

发明人： Eduard Cartier ,  Jerry Chen ,  Chao Zhao

IPC分类号： H01L29/94

CPC分类号： H01L21/28185 ,  C01G27/02 ,  C01P2002/72 ,  C23C16/40 ,  C23C16/405 ,  C23C16/4412 ,  H01B3/10 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/31604 ,  H01L28/40 ,  H01L29/517 ,  H01L29/518 ,  Y10T428/24917 ,  Y10T428/265

摘要： Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

摘要翻译： 公开了包含HfO 2 N 2和第二化合物的介电材料组合物。 组合物的特征在于至少一部分组合物为立方晶相。 此外，公开了包含这种介电材料化合物的基于半导体的器件及其形成方法。

公开(公告)号：US09419095B2

公开(公告)日：2016-08-16

申请号：US14119864

申请日：2012-12-12

申请人： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

发明人： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518

摘要： A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

摘要翻译： 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形 硅。

公开(公告)号：US09136160B2

公开(公告)日：2015-09-15

申请号：US13697372

申请日：2012-07-31

申请人： Lijun Dong ,  Chao Zhao

发明人： Lijun Dong ,  Chao Zhao

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L23/14 ,  H01L21/48

CPC分类号： H01L21/76802 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A solid hole array and a method for forming the same are disclosed. The solid hold array may comprise: substrate with a via; a top hole array base formed on a top surface of the substrate and a bottom hole array base formed on a bottom surface of the substrate, wherein a front hole is located in the top hole array base at a place corresponding to the via; and top protection layer formed on a surface and sidewalls of the top hole array base and a bottom protection layer formed on a surface of the bottom hole array base, wherein a rear window is located in the bottom hole array base and the bottom protection layer at a place corresponding to the via.

摘要翻译： 公开了一种固体孔阵列及其形成方法。 固体保持阵列可以包括：具有通孔的基底; 形成在所述基板的上表面上的顶孔阵列基座和形成在所述基板的底面的底孔阵列基座，其中，在与所述通孔相对应的位置处，所述顶孔阵列基座中的前孔位于所述顶孔阵列基底中; 以及形成在顶孔阵列基底的表面和侧壁上的顶部保护层和形成在底部孔阵列基底的表面上的底部保护层，其中后部窗口位于底部孔阵列基底中，底部保护层位于底部保护层 一个对应于通道的地方。

公开(公告)号：US09012965B2

公开(公告)日：2015-04-21

申请号：US13379120

申请日：2011-04-22

申请人： Jun Luo ,  Chao Zhao

发明人： Jun Luo ,  Chao Zhao

IPC分类号： H01L29/76 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/265

CPC分类号： H01L29/47 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/66643 ,  H01L29/7839

摘要： The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.

摘要翻译： 本发明公开了一种通过门最后工艺制造的新型MOSFET器件及其实现方法，该器件包括：衬底; 栅极叠层结构位于衬底的沟道区上，其任一侧消除了传统隔离间隔物; 构成源极/漏极区域的外延生长的超薄金属硅化物。 其中该器件消除了传统隔离间隔物下面的高电阻区域; 在源极/漏极和沟道区之间形成具有经过离子注入的掺杂剂偏析区域，这降低了金属硅化物源极/漏极与沟道之间的肖特基势垒高度。 同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。 根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

公开(公告)号：US08647987B2

公开(公告)日：2014-02-11

申请号：US13698283

申请日：2012-06-12

申请人： Tao Yang ,  Chao Zhao ,  Junfeng Li

发明人： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC分类号： H01L21/30625 ,  H01L21/31053 ,  H01L21/31056 ,  H01L22/26 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved.

摘要翻译： 本发明提供了一种改善化学机械平面化工艺的均匀性的方法，包括以下步骤：在基底上形成特征; 在所述特征之间形成第一绝缘隔离层; 平面化第一介电隔离层直到特征被暴露，使得特征之间的第一介电隔离层具有凹陷深度; 在特征和第一介电隔离层上形成第二绝缘隔离层，从而减小特征之间的第二介电隔离层与特征顶部的第二介电隔离层之间的高度差; 平坦化第二介电隔离层，直到特征被暴露。 根据本发明的化学机械平面化工艺的均匀性提高方法，在研磨特征顶部的介电隔离层之后再次形成介电隔离层，使得介电层之间的高度差 并且功能顶部的电介质层被有效地减少，并且特征的凹部得到补偿，从而有效地提高了模内均匀性。

公开(公告)号：US20140001646A1

公开(公告)日：2014-01-02

申请号：US13697372

申请日：2012-07-31

申请人： Lijun Dong ,  Chao Zhao

发明人： Lijun Dong ,  Chao Zhao

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L21/76802 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A solid hole array and a manufacture method thereof are provided. The method for manufacturing the solid hole array comprises: forming a top hole array base and a bottom hole array base on a top surface and a bottom surface of a substrate respectively; forming a front hole in the top hole array base; forming a top protection layer on the substrate with the top hole array base, and forming a bottom protection layer on the bottom hole array base; forming a rear window in the bottom hole array base and the bottom protection layer; and etching through the substrate by alkali corrosion to connect the front hole with the rear window. In addition, the present disclosure also provides a solid hole array. Using the method of the present disclosure, the intensity of the front film is enhanced, the process steps are simplified, the cost is decreased, and a large scale manufacture is more likely.

摘要翻译： 提供了一种固体孔阵列及其制造方法。 固体孔阵列的制造方法包括：分别在衬底的顶表面和底表面上形成顶孔阵列基底和底孔阵列基底; 在顶孔阵列基底中形成前孔; 在顶孔阵列基底上形成顶层保护层，在底孔阵列基底上形成底层保护层; 在底孔阵列基底和底部保护层中形成后窗; 并通过碱腐蚀蚀刻基板，将前孔与后窗连接起来。 此外，本公开还提供了一种固体孔阵列。 利用本公开的方法，提高了前膜的强度，简化了工艺步骤，降低了成本，并且更有可能进行大规模制造。