公开(公告)号：US08846488B2

公开(公告)日：2014-09-30

申请号：US13578598

申请日：2011-11-30

申请人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

发明人： Qingqing Liang ,  Huaxiang Yin ,  Huicai Zhong ,  Huilong Zhu

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/265

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L29/7842 ,  H01L29/7847

摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.

摘要翻译： 本发明涉及半导体器件及其制造方法。 根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分 引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。 根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

公开(公告)号：US08841777B2

公开(公告)日：2014-09-23

申请号：US12685954

申请日：2010-01-12

申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/40 ,  H01L21/20 ,  H01L27/06 ,  H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

公开(公告)号：US08829587B2

公开(公告)日：2014-09-09

申请号：US13003585

申请日：2010-09-19

申请人： Huilong Zhu

发明人： Huilong Zhu

IPC分类号： H01L29/768 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes a semiconductor substrate, a gate stack formed on the semiconductor substrate; a channel region below the gate stack; spacers outside the gate stack; and source/drain regions outside the channel region and in the semiconductor substrate, in which the gate stack includes a first gate dielectric layer on the channel region; a first conductive layer covering an upper surface of the first gate dielectric layer and inner walls of the spacers; a second gate dielectric layer covering a surface of the first conductive layer; and a second conductive layer covering a surface of the second gate dielectric layer. A method for manufacturing a flash memory device disclosed herein.

摘要翻译： 闪存器件包括半导体衬底，形成在半导体衬底上的栅叠层; 栅堆叠下方的沟道区; 栅极叠层之外的间隔物; 以及沟道区域和半导体衬底之外的源极/漏极区域，其中栅极堆叠层包括沟道区域上的第一栅极介电层; 覆盖所述第一栅极电介质层的上表面和所述间隔物的内壁的第一导电层; 覆盖所述第一导电层的表面的第二栅极介电层; 以及覆盖所述第二栅极介电层的表面的第二导电层。 本文公开的闪存器件的制造方法。

公开(公告)号：US08815698B2

公开(公告)日：2014-08-26

申请号：US13381636

申请日：2011-07-26

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/04 ,  H01L21/76 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66651

摘要： A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.

摘要翻译： 提供了半导体技术领域中的阱区形成方法和半导体基底。 一种方法包括：在半导体衬底中形成隔离区以隔离有源区; 选择所述有源区域中的至少一个，以及在所选择的有源区域中形成第一阱区域; 形成掩模以覆盖所选择的有源区，并蚀刻其余的有源区，以便形成沟槽; 并通过外延生长半导体材料以填充凹槽。 另一种方法包括：在半导体衬底中形成用于隔离有源区的隔离区; 在活跃区域形成井区; 蚀刻有源区以形成凹槽，使得凹槽具有小于或等于阱区深度的深度; 并通过外延生长半导体材料以填充凹槽。

公开(公告)号：US20140197410A1

公开(公告)日：2014-07-17

申请号：US13697096

申请日：2012-05-17

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L29/78 ,  H01L21/76283 ,  H01L29/04 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

摘要： The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region. The stressed layer provides a favorable stress to the channel of the semiconductor device, thus facilitating improving the performance of the semiconductor device.

摘要翻译： 本发明提供一种半导体结构的制造方法。 该方法包括：提供SOI衬底并在所述SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层的沟槽，所述沟槽部分地进入BOX层; 形成填充所述沟槽的一部分的应力层; 形成覆盖沟槽中的应力层的半导体层。 相应地，本发明还提供了通过上述方法形成的半导体结构。 在根据本发明的半导体结构及其制造方法中，在超薄SOI衬底上形成沟槽，首先填充有应力层，然后填充半导体材料以准备形成源极/漏极 地区。 应力层对半导体器件的通道提供有利的应力，从而有助于提高半导体器件的性能。

公开(公告)号：US20140154853A1

公开(公告)日：2014-06-05

申请号：US13878046

申请日：2012-12-07

申请人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

发明人： Qiuxia Xu ,  Huilong Zhu ,  Huajie Zhou ,  Gaobo Xu

IPC分类号： H01L29/66

CPC分类号： H01L21/28176 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

摘要翻译： 本公开公开了一种用于制造N型MOSFET的方法，包括：在半导体衬底上形成MOSFET的一部分，所述MOSFET的部分包括半导体衬底中的源极/漏极区，源/ 在半导体衬底之上的漏极区域和围绕替换栅极堆叠的栅极间隔; 去除MOSFET的替换栅极堆叠以形成暴露半导体衬底的表面的栅极开口; 在所述半导体的暴露表面上形成界面氧化物层; 在栅极开口中的界面氧化物层上形成高K栅极电介质层; 在高K栅极电介质层上形成第一金属栅极层; 将掺杂剂离子注入到第一金属栅极层中; 并且进行退火以使掺杂剂离子在高K栅极介电层和第一金属栅极层之间的上部界面以及高K栅极介电层和界面氧化物层之间的下部界面处扩散和积聚，并且还 通过界面反应在高K栅极介电层和界面氧化物层之间的下界面产生电偶极子。

公开(公告)号：US08729661B2

公开(公告)日：2014-05-20

申请号：US13379533

申请日：2011-04-25

申请人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

发明人： Zhijiong Luo ,  Haizhou Yin ,  Huilong Zhu

IPC分类号： H01L21/70

CPC分类号： H01L21/02647 ,  H01L21/02639 ,  H01L21/76229

摘要： A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

摘要翻译： 公开了一种半导体结构及其制造方法。 该方法包括：在第一半导体层上设置第一介电材料层并在第一介电材料层中限定开口; 通过限定在第一介电材料层中的开口在第一半导体层上外延生长第二半导体层，其中第二半导体层和第一半导体层包括彼此不同的材料; 以及在所述第二半导体层中形成所述第一介电材料层中所述开口的位置以及在相邻开口之间的中间位置处形成第二电介质材料的插塞。 根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

公开(公告)号：US08729638B2

公开(公告)日：2014-05-20

申请号：US13696071

申请日：2011-11-30

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7856 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator.

摘要翻译： 公开了一种用于制造FinFET和由其形成的半导体结构的方法，包括：在Si半导体衬底上提供SiGe层和SiGe层上的Si层，其中SiGe层的晶格常数与衬底的晶格常数相匹配; 图案化Si层和SiGe层以形成Fin结构; 在Fin结构的顶部和两侧上形成栅极堆叠以及围绕栅极堆叠的间隔物; 在间隔物作为掩模的同时，除去间隔物外部的Si层的一部分，同时保持间隔物内部的Si层的一部分; 去除在图案化之后保留的SiGe层的一部分，以形成空隙; 在空隙中形成绝缘体; 并在鳍结构和绝缘体的两侧外延生长应力源极和漏极区。

公开(公告)号：US08723021B2

公开(公告)日：2014-05-13

申请号：US13416354

申请日：2012-03-09

申请人： Harold J. Hovel ,  Rainer K. Krause ,  Zhengwen Li ,  Huilong Zhu

发明人： Harold J. Hovel ,  Rainer K. Krause ,  Zhengwen Li ,  Huilong Zhu

IPC分类号： H01L31/032

CPC分类号： G02B1/113 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/1868 ,  Y02E10/547 ,  Y02P70/521

摘要： A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer.

摘要翻译： 太阳能电池包括具有N区和P区的衬底，设置在衬底上的第一抗反射层，设置在第一抗反射层上的金属触点，设置在第一抗反射层上的第二抗反射层 抗反射层和金属接触，以及由第一抗反射层和第二抗反射层局部限定的区域，其具有扩散的金属接触材料，其可操作以通过第一抗反射层形成到衬底的导电路径， 金属触点和第二抗反射层。

公开(公告)号：US08710556B2

公开(公告)日：2014-04-29

申请号：US12937652

申请日：2010-06-25

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo ,  Qiagqing Liang

IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

摘要： The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.

摘要翻译： 本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离 翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。 半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。