公开(公告)号：US20240111092A1

公开(公告)日：2024-04-04

申请号：US17956757

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13

Abstract: Embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a PIC. In embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the PIC and the optical waveguide. In embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the PIC interacts with in a Plasmon effect to focus the light on to the optical waveguide. Other embodiments may be described and/or claimed.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20240078702A1

公开(公告)日：2024-03-07

申请号：US17902907

申请日：2022-09-05

Applicant: Intel Corporation

Inventor： Yi LI ,  Hong Seung YEON ,  Nicholas HAEHN ,  Wei LI ,  Raquel DE SOUZA BORGES FERREIRA ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN ,  Arnab ROY

IPC: G06T7/73 ,  H01L21/68 ,  H01L23/544

CPC classification number: G06T7/74 ,  H01L21/681 ,  H01L23/544 ,  G06T2207/20081 ,  G06T2207/30204 ,  H01L2223/54426

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

公开(公告)号：US20240021523A1

公开(公告)日：2024-01-18

申请号：US18374576

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5384 ,  H01L21/565 ,  H01L23/3107 ,  H01L25/50 ,  H01L23/562 ,  H01L21/6835 ,  H01L23/5386 ,  H01L21/486 ,  H01L21/4853 ,  H01L25/0652 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06558 ,  H01L2225/06548 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20230197660A1

公开(公告)日：2023-06-22

申请号：US17558297

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yue DENG ,  Jung Kyu HAN ,  Liang HE ,  Gang DUAN ,  Rahul N. MANEPALLI

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L24/13 ,  H01L23/49811 ,  H01L2224/16225 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2924/014

Abstract: A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.

公开(公告)号：US20230146165A1

公开(公告)日：2023-05-11

申请号：US18091989

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Yonggang LI ,  Sameer PAITAL

IPC: H01F27/26 ,  H01F27/42 ,  H01L21/768 ,  H01L23/64

CPC classification number: H01F27/26 ,  H01F27/425 ,  H01L21/76871 ,  H01L23/645 ,  H01F27/25

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

公开(公告)号：US20230092242A1

公开(公告)日：2023-03-23

申请号：US17507010

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Gang DUAN

IPC: H01L23/15 ,  H01L21/768

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20230091379A1

公开(公告)日：2023-03-23

申请号：US17482275

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Liang HE ,  Yeasir ARAFAT ,  Jung Kyu HAN ,  Ali LEHAF ,  Gang DUAN ,  Steve S. CHO ,  Yue DENG

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/528

Abstract: Embodiments disclosed herein include electronic packages with first level interconnects that comprise a first layer. In an embodiment, the electronic package comprises a package substrate and a pad on the package substrate. In an embodiment, the pad comprises copper. In an embodiment, a first layer is over the pad. In an embodiment, the first layer comprises iron. In an embodiment, a solder is over the first layer, and a die is coupled to the package substrate by the solder.

公开(公告)号：US20230088392A1

公开(公告)日：2023-03-23

申请号：US17481258

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Rahul N. MANEPALLI ,  Ravindra TANIKELLA ,  Sameer PAITAL

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.

公开(公告)号：US20230087838A1

公开(公告)日：2023-03-23

申请号：US17479033

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Rahul N. MANEPALLI ,  Srinivas V. PIETAMBARAM ,  Ravindra TANIKELLA ,  Sameer PAITAL ,  Gang DUAN

IPC: H01L23/29 ,  C03C17/32

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.