公开(公告)号：US20190088747A1

公开(公告)日：2019-03-21

申请号：US16198725

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Niti GOEL ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Marko RADOSAVLIJEVIC ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/20

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US20180158933A1

公开(公告)日：2018-06-07

申请号：US15576468

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG ,  Ashish AGRAWAL ,  Matthew V. METZ ,  Willy RACHMADY ,  Marc C. FRENCH ,  Jack T. KAVALIEROS ,  Rafael RIOS ,  Seiyon KIM ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  James M. POWERS ,  Sherry R. TAFT

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

公开(公告)号：US20180145077A1

公开(公告)日：2018-05-24

申请号：US15574820

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Anand S. MURTHY ,  Tahir GHANI ,  Willy RACHMADY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Glenn A. GLASS

IPC: H01L27/092 ,  H01L29/205 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/8258 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：US20180138289A1

公开(公告)日：2018-05-17

申请号：US15576666

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Jack T. KAVALIEROS ,  Sanaz K. GARDNER

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L27/092

CPC classification number: H01L29/6681 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/30612 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7853

Abstract: An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body including a plurality of nanowires including a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and a gate stack disposed on the channel region, the gate stack including a gate electrode disposed on a gate dielectric. A method of including forming a plurality of nanowires in separate planes on a substrate, each of the plurality of nanowires including a germanium material and separated from an adjacent nanowire by a sacrificial material; disposing a gate stack on the plurality of nanowires in a designated channel region, the gate stack including a dielectric material and a gate electrode.

公开(公告)号：US20170317187A1

公开(公告)日：2017-11-02

申请号：US15528793

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Marc C. FRENCH ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20160276438A1

公开(公告)日：2016-09-22

申请号：US15036406

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Abstract translation: 公开了用于在具有多纵横比掩模的不同基板上形成无缺陷半导体结构的技术。 多纵横比掩模包括形成在基板上的第一，第二和第三层。 第二层分别具有比第一和第三层中的第一开口和第三开口更宽的第二开口。 所有三个开口沿着共同的中心轴线居中。 半导体材料从衬底的顶表面生长并横向放置在第二开口内的第一层的顶表面上。 通过使用第三层作为蚀刻掩模来蚀刻设置在第三开口内并垂直于第三开口下方的半导体材料，使得横向溢出到第一层的顶表面上的剩余材料形成剩余结构。