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503 条记录 (耗时 0.032 秒)

    Mask material conversion
    71.
    发明申请
    Mask material conversion 有权

    公开(公告)号：US20060046200A1

    公开(公告)日：2006-03-02

    申请号：US10932993

    申请日：2004-09-01

    申请人： Mirzafer Abatchev ,  Gurtej Sandhu

    发明人： Mirzafer Abatchev ,  Gurtej Sandhu

    IPC分类号： G03F7/00

    CPC分类号： H01L21/308 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

    摘要： The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.

    Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate
    72.
    发明申请
    Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate 有权

    公开(公告)号：US20060040056A1

    公开(公告)日：2006-02-23

    申请号：US11257946

    申请日：2005-10-24

    申请人： Gurtej Sandhu

    发明人： Gurtej Sandhu

    IPC分类号： C23C16/00

    CPC分类号： H01L21/02181 ,  C23C16/0236 ,  C23C16/45531 ,  H01L21/02178 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/517

    摘要： The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate within a chamber from a gaseous first precursor. The first species monolayer is discontinuously formed over the substrate. The substrate having the discontinuous first species monolayer is exposed to a gaseous second precursor different from the first precursor effective to react with the first species to form a second species monolayer, and effective to form a reaction product of the second precursor with substrate material not covered by the first species monolayer. The substrate having the second species monolayer and the reaction product is exposed to a third gaseous substance different from the first and second precursors effective to selectively remove the reaction product from the substrate relative to the second species monolayer. Other implementations are contemplated.

    High throughput ILD fill process for high aspect ratio gap fill
    73.
    发明申请
    High throughput ILD fill process for high aspect ratio gap fill 审中-公开
    高通量ILD填充过程，用于高纵横比间隙填充

    公开(公告)号：US20060029745A1

    公开(公告)日：2006-02-09

    申请号：US10470618

    申请日：2003-01-02

    申请人： Gurtej Sandhu

    发明人： Gurtej Sandhu

    IPC分类号： H05H1/24 ,  B44C1/22 ,  C23C16/00

    CPC分类号： H01L21/02274 ,  C23C16/045 ,  C23C16/401 ,  C23C16/402 ,  C23C16/505 ,  H01J37/321 ,  H01J2237/3327 ,  H01L21/02164 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/76224

    摘要： A method for filling gaps in high aspect ratio patterned features on an integrated circuit using plasma CVD processes. A plasma is generated by an inert gas and process gases including silicon and oxygen components. The plasma causes the product gases to react and deposit onto the substrate and concurrently etch the deposited film. During an initial stage, the net deposition rate is kept low to improve filling of the high aspect ratio features, while during one or more later stages the net deposition rate is increased to provide a more conformal film at a higher throughput.

    摘要翻译： 一种使用等离子体CVD工艺在集成电路上填充高纵横比图案特征的间隙的方法。 通过惰性气体和包括硅和氧组分的工艺气体产生等离子体。 等离子体使产物气体反应并沉积到基底上并同时蚀刻沉积的膜。 在初始阶段期间，净沉积速率保持较低以改善高纵横比特征的填充，而在一个或多个后续阶段期间，净沉积速率增加以提供更高生产量的更保形膜。

    Methods of forming patterned photoresist layers over semiconductor substrates
    76.
    发明申请
    Methods of forming patterned photoresist layers over semiconductor substrates 有权
    在半导体衬底上形成图案化光致抗蚀剂层的方法

    公开(公告)号：US20050287816A1

    公开(公告)日：2005-12-29

    申请号：US10879367

    申请日：2004-06-28

    申请人： Guy Blalock ,  Gurtej Sandhu ,  Jon Daley

    发明人： Guy Blalock ,  Gurtej Sandhu ,  Jon Daley

    IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/31 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： G03F7/091 ,  H01L21/0276

    摘要： This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is formed over a semiconductor substrate. A photoresist footer-reducing fluid is provided within pores of the porous antireflective coating. A positive photoresist is formed over the porous antireflective coating having the fluid therein. The positive photoresist is patterned and developed to form a patterned photoresist layer, with the fluid within the pores being effective to reduce photoresist footing in the patterned photoresist layer than would otherwise occur in the absence of the fluid within the pores. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括在半导体衬底上形成图案化光致抗蚀剂层的方法。 在一个实施方案中，在半导体衬底上形成多孔抗反射涂层。 在多孔抗反射涂层的孔内提供光致抗蚀剂页脚还原液。 在其中具有流体的多孔抗反射涂层上形成正性光致抗蚀剂。 正性光致抗蚀剂被图案化和显影以形成图案化的光致抗蚀剂层，孔内的流体有效地减少图案化光致抗蚀剂层中的光致抗蚀剂底脚，而不是在孔内不存在流体的情况下发生。 考虑了其他方面和实现。

    Gated field effect devices
    77.
    发明申请
    Gated field effect devices 有权
    门控场效应器件

    公开(公告)号：US20050269648A1

    公开(公告)日：2005-12-08

    申请号：US10861744

    申请日：2004-06-04

    申请人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej Sandhu ,  Kunal Parekh

    发明人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej Sandhu ,  Kunal Parekh

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Boron incorporated diffusion barrier material
    78.
    发明申请
    Boron incorporated diffusion barrier material 有权
    硼掺入扩散阻挡材料

    公开(公告)号：US20050266624A1

    公开(公告)日：2005-12-01

    申请号：US11119370

    申请日：2005-04-29

    申请人： Vishnu Agarwal ,  Gurtej Sandhu

    发明人： Vishnu Agarwal ,  Gurtej Sandhu

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49

    CPC分类号： H01L21/28088 ,  H01L21/28061 ,  H01L21/76841 ,  H01L23/53257 ,  H01L29/4941 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

    摘要翻译： 公开了一种包括TiN x B B y y的扩散阻挡层，用于保护集成晶体管中的栅极氧化物层。 可以通过首先形成TiN层然后将硼掺入到TiN层中来制造扩散阻挡层。 扩散阻挡层也可以通过使用包括硼的TDMAT工艺来形成TiN层的方法来制造。 扩散阻挡层也可以通过使用CVD工艺形成TiN x B层Y 3层来制造。 扩散阻挡层特别适用于通过CVD形成的钨或硅化钨导电层。

    Methods for forming conductive structures and structures regarding same
    80.
    发明申请
    Methods for forming conductive structures and structures regarding same 失效
    形成导电结构和结构的方法

    公开(公告)号：US20050230735A1

    公开(公告)日：2005-10-20

    申请号：US11146827

    申请日：2005-06-07

    申请人： Cem Basceri ,  Gurtej Sandhu

    发明人： Cem Basceri ,  Gurtej Sandhu

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L28/75 ,  H01L21/76888 ,  H01L28/55 ,  H01L28/84

    摘要： A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the metal oxide regions are formed by diffusion of oxygen through grain boundaries of the metal layer, e.g., platinum, to oxidize a metal layer thereon, e.g, ruthenium layer. The structure is particularly advantageous for use in capacitor structures and memory devices, such as dynamic random access memory (DRAM) devices.

    摘要翻译： 一种形成金属/金属氧化物结构的方法，其包括在金属层例如铂的晶界处形成金属氧化物区域，例如氧化钌区域。 优选地，金属氧化物区域通过氧气通过金属层例如铂的晶界的扩散而形成，以氧化其上的金属层，例如钌层。 该结构对于用于诸如动态随机存取存储器（DRAM）器件的电容器结构和存储器件尤为有利。