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117 条记录 (耗时 0.039 秒)

    Integrated circuit interconnect structure
    71.
    发明授权
    Integrated circuit interconnect structure 有权
    集成电路互连结构

    公开(公告)号：US08237286B2

    公开(公告)日：2012-08-07

    申请号：US12760594

    申请日：2010-04-15

    申请人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    发明人： Hanyi Ding ,  Ronald G. Filippi ,  Jong-Ru Guo ,  Ping-Chuan Wang

    IPC分类号： H01L23/522

    CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line.

    摘要翻译： 一种集成电路（IC）互连结构，其包括位于电介质中并且在一端耦合到高电流器件的第一通孔和位于电介质中的缓冲金属段，并在其相对端耦合到第一通孔。 缓冲金属段包括在其上形成ILD干酪糖化图案的多个电绝缘介电层（ILD）焊盘以引导电流。 IC互连结构还包括位于介质上的第二通孔，该电介质形成在缓冲金属段上并且在一端耦合到缓冲金属段，并且金属电源线形成在电介质中，并在其相对端耦合到第二通孔。 缓冲金属片段上的ILD焊盘的使用使得能够沿着金属电源线更均匀地分布电流。

    Test structure for determination of TSV depth
    72.
    发明授权
    Test structure for determination of TSV depth 有权
    用于测定TSV深度的测试结构

    公开(公告)号：US08232115B2

    公开(公告)日：2012-07-31

    申请号：US12566726

    申请日：2009-09-25

    申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H01L21/66

    CPC分类号： H01L22/34 ,  H01L21/76898

    摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

    摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括所述第一TSV，电连接到所述第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。

    Method, structure, and design structure for a through-silicon-via Wilkinson power divider
    73.
    发明授权
    Method, structure, and design structure for a through-silicon-via Wilkinson power divider 有权
    通过硅片通过威尔金森功率分配器的方法，结构和设计结构

    公开(公告)号：US08216912B2

    公开(公告)日：2012-07-10

    申请号：US12548033

    申请日：2009-08-26

    申请人： Hanyi Ding ,  Alvin J. Joseph ,  Wayne H. Woods, Jr.

    发明人： Hanyi Ding ,  Alvin J. Joseph ,  Wayne H. Woods, Jr.

    IPC分类号： H01L21/20 ,  H01L21/44

    CPC分类号： G06F17/5077 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P5/16 ,  H01P11/007 ,  H01L2924/00

    摘要： A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

    摘要翻译： 一种通过硅通孔威尔金森功率分配器的方法，结构和设计结构。 一种方法包括：在基板的第一侧上形成输入; 形成包括在所述基板中形成的第一穿通硅通孔的第一支脚，其中所述第一支路电连接所述输入端和第一输出端; 形成包括形成在所述基板中的第二通硅通孔的第二支脚，其中所述第二支脚电连接所述输入端和第二输出端，以及形成电连接在所述第一输出端和所述第二输出端之间的电阻器。

    Methods of fabricating coplanar waveguide structures
    75.
    发明授权
    Methods of fabricating coplanar waveguide structures 有权
    制造共面波导结构的方法

    公开(公告)号：US08028406B2

    公开(公告)日：2011-10-04

    申请号：US12061861

    申请日：2008-04-03

    申请人： Hanyi Ding ,  Essam F. Mina ,  Guoan Wang ,  Wayne H. Woods

    发明人： Hanyi Ding ,  Essam F. Mina ,  Guoan Wang ,  Wayne H. Woods

    IPC分类号： H05K3/10 ,  H01P11/00 ,  H01P3/00

    CPC分类号： H01P11/003 ,  H01P3/003 ,  Y10T29/49016 ,  Y10T29/49155 ,  Y10T29/49162

    摘要： Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array. Each of the second plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.

    摘要翻译： 制造共面波导结构的方法。 该方法可以包括在第一和第二接地导体之间的共面布置中形成第一和第二接地导体和信号导体，在信号导体和第一和第二接地导体之上形成基本上平行的屏蔽导体的第一共面阵列，并形成 在信号导体和第一和第二接地导体下面的基本上平行的屏蔽导体的第二共面阵列。 该方法还包括形成位于信号导体和第一接地导体之间横向定位的第一多个导电桥，以及形成位于信号导体和第二接地导体之间横向定位的第二多个导电桥。 第一多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。 第二多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。

    Chip Inductor With Frequency Dependent Inductance
    76.
    发明申请
    Chip Inductor With Frequency Dependent Inductance 有权
    具有频率依赖电感的片式电感器

    公开(公告)号：US20100237464A1

    公开(公告)日：2010-09-23

    申请号：US12632030

    申请日：2009-12-07

    申请人： Hanyi Ding ,  Wayne H. Woods, JR.

    发明人： Hanyi Ding ,  Wayne H. Woods, JR.

    IPC分类号： H01L27/06 ,  G06F17/50

    CPC分类号： H01L28/10 ,  G06F17/5068 ,  G06F17/5077 ,  H01L21/31053 ,  H01L21/76808 ,  H01L21/76826 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L29/432 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

    摘要翻译： 包括信号传输金属线和电容接地感应信号耦合金属线的一组金属线结构被嵌入在电介质材料层中。 电容器串联连接在电容接地的感应信号耦合金属线路和可能在输入侧或输出侧的局部电接地之间。 金属线结构和电容集合提供了一个频率相关的电感。 频率依赖电感器的Q因子具有多个峰值，使得能够在多个频率下操作频率相关的电感器。 可以在频率相关电感器中提供多个电容耦合的感应信号耦合金属线路，每个电路通过电容器连接到本地电接地。 通过选择电容器的不同电容值，可以在不同信号频率的频率相关电感器中获得Q因子的多个值。