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公开(公告)号：US20120012835A1
公开(公告)日：2012-01-19
申请号：US12836217
申请日：2010-07-14
IPC分类号： H01L29/786 , H01L21/34 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02581 , H01L29/66969
摘要： A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.
摘要翻译： 顶栅和底栅薄膜晶体管（TFT）具有相关的制造方法。 TFT由衬底和覆盖衬底的活性金属氧化物半导体（MOS）层制成。 源极/漏极（S / D）区域形成为与有源MOS层接触。 沟道区域插入在S / D区域之间。 TFT包括栅极电极和介于沟道区域和栅电极之间的栅极电介质。 有源MOS层可以是ZnOx，InOx，GaOx，SnOx或上述材料的组合。 有源MOS层还包括主要掺杂剂如H，K，Sc，La，Mo，Bi，Ce，Pr，Nd，Sm，Dy或上述掺杂剂的组合。 有源MOS层还可以包括第二掺杂剂。
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72.发明授权Fabrication of a semiconductor nanoparticle embedded insulating film electroluminescence device 有权半导体纳米颗粒嵌入式绝缘膜电致发光器件的制造公开(公告)号：US08007332B2
公开(公告)日：2011-08-30
申请号：US12187605
申请日：2008-08-07
IPC分类号： H01J9/24
CPC分类号： C23C16/30 , C23C16/24 , C23C16/401 , C23C16/402 , C23C16/505 , C23C16/56 , H01L21/0214 , H01L21/02274 , H01L21/02321 , H01L21/0234 , H01L21/02532 , H01L21/02601 , H01L21/0262 , H01L21/31608 , H01L33/18
摘要： A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm2) at an applied electric field lower than 3 MV/cm. In another aspect, the annealed semiconductor nanoparticle embedded Si insulating film has an index of refraction (n) in a range of 1.8-3.0, as measured at 632 nm, with a current density of greater than 1 A/cm2 at an applied electric field lower than 3 MV/cm.
摘要翻译： 提供了一种用于制造用于电致发光（EL）应用的半导体纳米颗粒嵌入的Si绝缘膜的方法。 该方法提供底部电极，并且沉积半导体纳米颗粒嵌入的Si绝缘膜，其包括选自N和C组成的组的元素，覆盖在底部电极上。 在退火之后，形成半导体纳米颗粒嵌入的Si绝缘膜，其消光系数（k）在0.01〜1.0的范围内，在大约632纳米（nm）测量，电流密度（J）大于1安培 在施加的电场低于3MV / cm下的平方厘米（A / cm 2）。 在另一方面，被退火的半导体纳米颗粒嵌入的Si绝缘膜的折射率（n）在632nm处测量的范围为1.8-3.0，在施加的电场下的电流密度大于1A / cm 2 低于3 MV / cm。
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公开(公告)号：US07916986B2
公开(公告)日：2011-03-29
申请号：US12112767
申请日：2008-04-30
CPC分类号： C23C16/30 , C23C16/56 , H01L21/02156 , H01L21/02164 , H01L21/02274 , H01L21/02321 , H01L21/02362 , H01L21/31608
摘要： An erbium (Er)-doped silicon (Si) nanocrystalline embedded silicon oxide (SiOx) waveguide and associated fabrication method are presented. The method provides a bottom layer, and forms an Er-doped Si nanocrystalline embedded SiOx film waveguide overlying the bottom layer, having a minimum optical attenuation at about 1540 nanometers (nm). Then, a top layer is formed overlying the Er-doped SiOx film. The Er-doped SiOx film is formed by depositing a silicon rich silicon oxide (SRSO) film using a high density plasma chemical vapor deposition (HDPCVD) process and annealing the SRSO film. After implanting Er+ ions, the Er-doped SiOx film is annealed again. The Er-doped Si nanocrystalline SiOx film includes has a first refractive index (n) in the range of 1.46 to 2.30. The top and bottom layers have a second refractive index, less than the first refractive index.
摘要翻译： 提出了一种铒（Er）掺杂的硅（Si）纳米晶体嵌入式氧化硅（SiOx）波导及其制造方法。 该方法提供底层，并且形成覆盖底层的掺铒Si纳米晶体的包含SiOx的薄膜波导，在约1540纳米（nm）处具有最小的光衰减。 然后，形成覆盖Er掺杂的SiOx膜的顶层。 通过使用高密度等离子体化学气相沉积（HDPCVD）方法沉积富硅氧化物（SRSO）膜并退火SRSO膜来形成Er掺杂的SiOx膜。 在注入Er +离子后，再次对Er掺杂的SiOx膜进行退火。 掺铒Si纳米晶SiOx膜的第一折射率（n）在1.46〜2.30的范围内。 顶层和底层具有小于第一折射率的第二折射率。
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公开(公告)号：US07786021B2
公开(公告)日：2010-08-31
申请号：US11264979
申请日：2005-11-02
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/4908 , H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/28008 , H01L21/31612 , H01L29/6675 , H01L29/78642
摘要： A thin-film transistor (TFT) with a multilayer gate insulator is provided, along with a method for forming the same. The method comprises: forming a channel, first source/drain (S/D) region, and a second S/D region in a Silicon (Si) active layer; using a high-density plasma (HDP) source, growing a first layer of Silicon oxide (SiOx) from the Si active layer, to a first thickness, where x is less than, or equal to 2; depositing a second layer of SiOx having a second thickness, greater than the first thickness, overlying the first layer of SiOx; using the HDP source, additionally oxidizing the second layer of SiOx, wherein the first and second SiOx layers form a gate insulator; and, forming a gate electrode adjacent the gate insulator. In one aspect, the second Si oxide layer is deposited using a plasma-enhanced chemical vapor deposition (PECVD) process with tetraethylorthosilicate (TEOS) precursors.
摘要翻译： 提供具有多层栅极绝缘体的薄膜晶体管（TFT）及其形成方法。 该方法包括：在硅（Si）有源层中形成沟道，第一源/漏（S / D）区和第二S / D区; 使用高密度等离子体（HDP）源，从Si活性层生长第一层氧化硅（SiO x）至第一厚度，其中x小于或等于2; 在SiOx的第一层上沉积具有大于第一厚度的第二厚度的第二SiO x层; 使用HDP源，另外氧化SiO x的第二层，其中第一和第二SiO x层形成栅极绝缘体; 并且形成与栅极绝缘体相邻的栅电极。 在一个方面，使用等离子体增强化学气相沉积（PECVD）法与原硅酸四乙酯（TEOS）前体沉积第二Si氧化物层。
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75.发明申请Directionally Annealed Silicon Film Having a (100)-Normal Crystallographical Orientation 审中-公开具有（100） - 正常晶体取向的定向退火硅膜公开(公告)号：US20100102323A1
公开(公告)日：2010-04-29
申请号：US12258363
申请日：2008-10-24
CPC分类号： H01L21/02609 , H01L21/02422 , H01L21/02532 , H01L21/02675 , H01L27/1285
摘要： A method is provided for forming a directionally crystallized (100)-normal crystallographic orientation silicon (Si) film. The method provides a substrate including Si. An amorphous Si (a-Si) layer is formed overlying the substrate, and a silicon oxide cap layer is formed overlying the a-Si layer. In response to scanning a laser in a first direction along a top surface of the silicon oxide cap layer, the a-Si layer is transformed into a crystalline Si film having a (100)-normal crystallographic orientation, with crystal grains elongated in the first direction. That is, the crystalline Si film has grain boundaries between crystal grains, aligned in parallel with the first direction.
摘要翻译： 提供了一种用于形成定向结晶（100） - 正常晶体取向硅（Si）膜的方法。 该方法提供包括Si的衬底。 在衬底上形成非晶Si（a-Si）层，并且形成覆盖a-Si层的氧化硅覆盖层。 响应于沿着氧化硅盖层的顶表面沿第一方向扫描激光器，将a-Si层转变为具有（100） - 正常结晶取向的晶体Si膜，其中晶粒在第一 方向。 也就是说，晶体Si膜在晶粒之间具有与第一方向平行排列的晶界。
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公开(公告)号：US07608144B2
公开(公告)日：2009-10-27
申请号：US11263604
申请日：2005-10-31
IPC分类号： C30B1/04
CPC分类号： H01L21/02686 , C30B13/00 , C30B13/24 , C30B29/06 , H01L21/02532 , H01L21/2022 , H01L21/2026 , H01L27/1285
摘要： A process of lateral crystallization is provided for increasing the lateral growth length (LGL). A localized region of the substrate is heated for a short period of time. While the localized region of the substrate is still heated, a silicon film overlying the substrate is irradiated to anneal the silicon film to crystallize a portion of the silicon film in thermal contact with the heated substrate region. A CO2 laser may be used as a heat source to heat the substrate, while a UV laser or a visible spectrum laser is used to irradiate and crystallize the film.
摘要翻译： 提供横向结晶的方法用于增加横向生长长度（LGL）。 将衬底的局部区域加热一段短时间。 当衬底的局部区域仍被加热时，照射覆盖在衬底上的硅膜来退火硅膜，以使与加热的衬底区域热接触的一部分硅膜结晶。 可以使用CO2激光器作为加热基板的热源，而使用UV激光或可见光谱激光来照射和结晶膜。
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公开(公告)号：US07532187B2
公开(公告)日：2009-05-12
申请号：US11184699
申请日：2005-07-18
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.
摘要翻译： 提供了双栅极薄膜晶体管（DG-TFT）电压存储电路。 电路包括电压存储元件，具有连接到数据线的第一源极/漏极（S / D）的DG-TFT，连接到第一栅极线的顶栅极，连接到电压存储器的第二S / D区域 元件和连接到偏置线的底栅。 在一个方面，电路还包括具有连接到第一栅极线的输入的电压移位器和用于在偏置线上提供偏置电压的输出。 电压存储元件的实例包括电容器，液晶（LC）像素和发光二极管（LED）像素。
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78.发明申请Fabrication of a Semiconductor Nanoparticle Embedded Insulating Film Electroluminescence Device 有权半导体纳米颗粒嵌入式绝缘膜电致发光器件的制造公开(公告)号：US20090115311A1
公开(公告)日：2009-05-07
申请号：US12187605
申请日：2008-08-07
CPC分类号： C23C16/30 , C23C16/24 , C23C16/401 , C23C16/402 , C23C16/505 , C23C16/56 , H01L21/0214 , H01L21/02274 , H01L21/02321 , H01L21/0234 , H01L21/02532 , H01L21/02601 , H01L21/0262 , H01L21/31608 , H01L33/18
摘要： A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm2) at an applied electric field lower than 3 MV/cm. In another aspect, the annealed semiconductor nanoparticle embedded Si insulating film has an index of refraction (n) in a range of 1.8-3.0, as measured at 632 nm, with a current density of greater than 1 A/cm2 at an applied electric field lower than 3 MV/cm.
摘要翻译： 提供了一种用于制造用于电致发光（EL）应用的半导体纳米颗粒嵌入的Si绝缘膜的方法。 该方法提供底部电极，并且沉积半导体纳米颗粒嵌入的Si绝缘膜，其包括选自N和C组成的组的元素，覆盖在底部电极上。 在退火之后，形成半导体纳米颗粒嵌入的Si绝缘膜，其消光系数（k）在0.01〜1.0的范围内，在大约632纳米（nm）测量，电流密度（J）大于1安培 在施加的电场低于3MV / cm下的平方厘米（A / cm 2）。 在另一方面，被退火的半导体纳米颗粒嵌入的Si绝缘膜的折射率（n）在632nm处测量的范围为1.8-3.0，在施加的电场下的电流密度大于1A / cm 2 低于3 MV / cm。
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公开(公告)号：US07446023B2
公开(公告)日：2008-11-04
申请号：US11013605
申请日：2004-12-15
IPC分类号： H01L21/332
CPC分类号： H01L21/02164 , C23C16/24 , C23C16/45523 , C23C16/509 , H01L21/022 , H01L21/02274 , H01L21/02323 , H01L21/0234 , H01L21/02381 , H01L21/0242 , H01L21/02422 , H01L21/0245 , H01L21/02532 , H01L21/28194 , H01L21/28211 , H01L21/3003 , H01L21/31612 , H01L29/4908 , H01L29/513 , H01L29/78609
摘要： A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si)/oxide stack layer; plasma oxidizing the Si/oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si/oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.
摘要翻译： 提供了高密度等离子体加氢方法。 通常，该方法包括：形成硅（Si）/氧化物堆叠层; 使用诸如电感耦合等离子体（ICP）源的高密度等离子体源，在小于400℃的温度下等离子体氧化Si /氧化物堆叠; 在系统压力高达500毫托的地方引入包括H2的气氛; 使用高密度等离子体源在小于400摄氏度的温度下对叠层进行氢化; 并形成覆盖氧化物的电极。 电极可以在氢化之前或之后形成。 Si /氧化物堆叠可以以多种方式形成。 在一个方面，使用ICP源形成Si层，并且在低于400℃的温度下对硅层进行等离子体氧化。 氧化物形成，附加氧化和氢化步骤可以在公共室中原位进行。
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公开(公告)号：US20080246088A1
公开(公告)日：2008-10-09
申请号：US12140017
申请日：2008-06-16
IPC分类号： H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译： 提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。 该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。 沟槽有一个底部和侧壁。 在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。 然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。 替代地，LDD长度与沟槽的深度直接相关。
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