公开(公告)号：US07253102B2

公开(公告)日：2007-08-07

申请号：US10860341

申请日：2004-06-02

申请人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

发明人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L28/82 ,  H01L28/55

摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。

公开(公告)号：US20060154382A1

公开(公告)日：2006-07-13

申请号：US11346676

申请日：2006-02-03

申请人： Cem Basceri ,  Gurtej Sandhu ,  Mark Visokay

发明人： Cem Basceri ,  Gurtej Sandhu ,  Mark Visokay

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L28/56 ,  H01L27/10811

摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1-x)TiO3, and methods of making such capacitors and DRAM cells are provided. One method includes providing a conductive oxide electrode, oxidizing at least the upper surface of the conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.

摘要翻译： 使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元 ）和提供制造这种电容器和DRAM单元的方法。 一种方法包括提供导电氧化物电极，至少氧化导电氧化物电极的上表面，在导电氧化物电极上沉积高介电常数氧化物电介质材料的第一层，氧化高介电常数氧化物电介质的第一层 在氧化条件下的材料，在所述电介质的第一层上沉积高介电常数氧化物介电材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

公开(公告)号：US07038263B2

公开(公告)日：2006-05-02

申请号：US10850664

申请日：2004-05-21

申请人： Haining Yang ,  Dan Gealy ,  Gurtej S. Sandhu ,  Howard Rhodes ,  Mark Visokay

发明人： Haining Yang ,  Dan Gealy ,  Gurtej S. Sandhu ,  Howard Rhodes ,  Mark Visokay

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： A structure and method are disclosed for forming a capacitor for an integrated circuit. The capacitor includes a rhodium-rich structure, a rhodium oxide layer in direct contact with the rhodium-rich structure, a capacitor dielectric in direct contact with the rhodium oxide layer and a top electrode over the capacitor. The rhodium-rich structure can include rhodium alloys and the capacitor dielectric preferably has a high dielectric constant.

摘要翻译： 公开了一种用于形成用于集成电路的电容器的结构和方法。 电容器包括富铑结构，与富铑结构直接接触的铑氧化物层，与氧化铑层直接接触的电容器电介质和电容器上的顶电极。 富铑结构可以包括铑合金，并且电容器电介质优选具有高的介电常数。

公开(公告)号：US20050079655A1

公开(公告)日：2005-04-14

申请号：US10681399

申请日：2003-10-08

申请人： Yuanning Chen ,  Mark Visokay

发明人： Yuanning Chen ,  Mark Visokay

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/332 ,  H01L21/336

CPC分类号： H01L21/28247 ,  H01L21/31122 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/6656 ,  H01L29/6659

摘要： A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

摘要翻译： 半导体器件包括接触栅极结构的栅极的相对侧表面的偏置间隔物。 可以通过在栅极和半导体衬底上选择性地沉积氧化物层来形成偏移间隔物，使得栅极e的相对侧表面基本上不含氧化物层。 然后可以形成接触栅极的相对侧表面的偏移间隔物。

公开(公告)号：US20050066895A1

公开(公告)日：2005-03-31

申请号：US10991693

申请日：2004-11-18

申请人： Weimin Li ,  Mark Visokay

发明人： Weimin Li ,  Mark Visokay

IPC分类号： C23C16/02 ,  C23C16/18 ,  C23C16/44 ,  C23C16/455 ,  H01L21/285 ,  C23C16/00

CPC分类号： C23C16/45523 ,  C23C16/0281 ,  C23C16/18 ,  H01L21/28556

摘要： A method and system for performing metal-organic chemical vapor deposition (MOCVD). The method introduces a metal-organic compound into the CVD chamber in the presence of a first reactant selected to have a reducing chemistry and then, subsequently, a second reactant selected to have an oxidizing chemistry. The reducing chemistry results in deposition of metal species having a reduced surface mobility creating more uniform coverage and better adhesion. The oxidizing species results in deposition of metal species having a greater surface mobility leading to greater surface agglomeration and faster growth. By alternating the two reacts, faster growth is achieved and uniformity of the metal structure is enhanced.

公开(公告)号：US06764943B2

公开(公告)日：2004-07-20

申请号：US10196535

申请日：2002-07-15

申请人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

发明人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

IPC分类号： H01L214763

CPC分类号： H01L28/82 ,  H01L28/55

摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/ruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌膜的情况下，蚀刻剂优先除去钌相，留下通过下面的导电层物理和电连接的氧化钌的凹陷或“孤立”的表面。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。

公开(公告)号：US06596583B2

公开(公告)日：2003-07-22

申请号：US10002906

申请日：2001-10-29

申请人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

发明人： Vishnu K. Agarwal ,  Garo Derderian ,  Gurtej S. Sandhu ,  Weimin M. Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

公开(公告)号：US06482736B1

公开(公告)日：2002-11-19

申请号：US09590791

申请日：2000-06-08

申请人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

发明人： Cem Basceri ,  Mark Visokay ,  Thomas M. Graettinger ,  Steven D. Cummings

IPC分类号： H01L2120

CPC分类号： H01L28/82 ,  H01L28/55

摘要： An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used. In the case of this etchant and a ruthenium/riruthenium oxide film, the etchant preferentially removes the ruthenium phase, leaving a pitted or “islanded” surface of ruthenium oxide physically and electrically connected by the underlying conductive layer. The remaining pitted or islanded layer, together with the underlying conductive layer, if any, constitutes an enhanced-surface-area conductive layer. The enhanced-surface-area conductive layer may be used to form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like.

摘要翻译： 与高介电常数材料兼容的增强表面积导电层是通过形成具有至少两个相的膜或层，其中至少一个导电层是导电的。 膜可以以任何方便的方式形成，例如通过化学气相沉积技术，其后可以进行退火以更好地限定和/或结晶至少两个相。 膜可以形成在下面的导电层上。 所述至少两个相中的至少一个相被选择性地从膜上移除，例如通过蚀刻工艺，其优先蚀刻至少两个相中的至少一个，以便留下导电相的至少一部分。 导电的钌和氧化钌可以用于两个或多个相。 也可以使用铱及其氧化物，铑及其氧化物，以及铂和铂 - 铑。 可以使用包含硝酸铈铵和乙酸的湿蚀刻剂。 在这种蚀刻剂和钌/氧化钌氧化物膜的情况下，蚀刻剂优先除去钌相，留下氧化钌的凹陷或“孤立”的表面通过下面的导电层物理和电连接。 剩余的凹陷或孤岛层与下面的导电层（如果有的话）一起构成增强的表面积导电层。 增强表面积导电层可用于在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。

公开(公告)号：US08183137B2

公开(公告)日：2012-05-22

申请号：US11752424

申请日：2007-05-23

申请人： Mark Visokay ,  Jorge Adrian Kittl

发明人： Mark Visokay ,  Jorge Adrian Kittl

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (210). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (230), wherein the NMOS gate structure (230) includes an NMOS gate dielectric (240) and an NMOS gate electrode (250). This method further includes forming n-type source/drain regions (710) within the substrate (210) proximate the NMOS gate structure (230), and siliciding the NMOS gate electrode (250) to form a silicided gate electrode (1110, 1210). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode (250) prior to or concurrently with siliciding.

摘要翻译： 因此，本公开提供了一种半导体器件及其制造方法。 在一个实施例中，用于制造半导体器件的方法包括在栅极电介质材料层上形成栅电极层，其中栅极电介质材料层位于衬底（210）上方。 该方法还包括将栅电极材料层和栅介电材料层图案化成NMOS栅极结构（230），其中NMOS栅极结构（230）包括NMOS栅极电介质（240）和NMOS栅电极（250） ）。 该方法还包括在靠近NMOS栅极结构（230）的基底（210）内形成n型源极/漏极区（710），以及硅化NMOS栅电极（250）以形成硅化栅电极（1110,1210） 。 该方法还包括在硅化之前或同时将p型掺杂剂放置在栅电极材料或NMOS栅电极（250）的层内。

公开(公告)号：US07276408B2

公开(公告)日：2007-10-02

申请号：US10681399

申请日：2003-10-08

申请人： Yuanning Chen ,  Mark Visokay

发明人： Yuanning Chen ,  Mark Visokay

IPC分类号： H01L21/8249

CPC分类号： H01L21/28247 ,  H01L21/31122 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/6656 ,  H01L29/6659

摘要： A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

摘要翻译： 半导体器件包括接触栅极结构的栅极的相对侧表面的偏置间隔物。 可以通过在栅极和半导体衬底上选择性地沉积氧化物层来形成偏移间隔物，使得栅极e的相对侧表面基本上不含氧化物层。 然后可以形成接触栅极的相对侧表面的偏移间隔物。