公开(公告)号：US20210074671A1

公开(公告)日：2021-03-11

申请号：US17099625

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/48

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

公开(公告)号：US20200373252A1

公开(公告)日：2020-11-26

申请号：US16993860

申请日：2020-08-14

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street ,  Wei Zhou ,  Christopher J. Gambee ,  Jonathan S. Hacker ,  Shijian Luo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

公开(公告)号：US10741528B2

公开(公告)日：2020-08-11

申请号：US16416625

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/552 ,  H01L23/48 ,  H01L25/00 ,  H01L23/04 ,  H01L23/36

Abstract: A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.

公开(公告)号：US20200219851A1

公开(公告)日：2020-07-09

申请号：US16823028

申请日：2020-03-18

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L25/065 ,  H01L23/495 ,  H01L23/48 ,  H01L25/00 ,  H01L23/64 ,  H01L21/56 ,  H01L23/36

Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

公开(公告)号：US20200168517A1

公开(公告)日：2020-05-28

申请号：US16775163

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC: H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00

Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.

公开(公告)号：US20190279967A1

公开(公告)日：2019-09-12

申请号：US16416625

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/552 ,  H01L25/00

Abstract: A semiconductor device includes a first die; a first metal enclosure directly contacting and vertically extending below the first die, wherein the first metal enclosure peripherally encircles a first enclosed space; a second die directly contacting the first metal enclosure opposite the first die; a second metal enclosure directly contacting and vertically extending below the second die, wherein the second metal enclosure peripherally encircles a second enclosed space; and an enclosure connection mechanism directly contacting the first metal enclosure and the second metal enclosure for electrically coupling the first metal enclosure and the second metal enclosure.

公开(公告)号：US20190109019A1

公开(公告)日：2019-04-11

申请号：US16203538

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Zhaohui Ma ,  Aibin Yu

IPC: H01L21/48 ,  H01L25/00 ,  H01L23/373 ,  H01L25/065 ,  H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L23/367 ,  H01L23/31 ,  H01L21/78

Abstract: Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.

公开(公告)号：US20160358898A1

公开(公告)日：2016-12-08

申请号：US14730681

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma ,  Sony Varghese ,  Jonathan S. Hacker ,  Bret K. Street ,  Shijian Luo

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die.

Abstract translation: 制造半导体器件封装的方法可以包括将第一半导体管芯附接到载体晶片，第一半导体管芯的面向载体晶片的非活性表面。 一个或多个附加的半导体管芯可以在第一半导体管芯上与第一半导体管芯的与载体晶片相对的一侧堆叠以形成半导体管芯堆叠。 保护材料可以位于半导体管芯的堆叠之上，保护材料的一部分沿着第一半导体管芯的侧表面延伸到接近第一半导体管芯的非活性表面的位置。 载体晶片可以与第一半导体管芯分离。

公开(公告)号：US20160233110A1

公开(公告)日：2016-08-11

申请号：US15134788

申请日：2016-04-21

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Zhaohui Ma ,  Aibin Yu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/4882 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/4334 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/29191 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

公开(公告)号：US20160079094A1

公开(公告)日：2016-03-17

申请号：US14485973

申请日：2014-09-15

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/324 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/565 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. Processing systems and in-process semiconductor wafers are also disclosed.

Abstract translation: 处理半导体晶片的方法可以包括例如封装半导体材料晶片的活性表面和每个侧表面，位于晶片的有效表面上的多个半导体器件，位于 晶片的背面表面和载体基板的侧表面的至少一部分通过胶粘材料固定在晶片上。 粘合剂材料的侧表面的至少一部分可以通过去除包封材料的至少一部分而暴露。 载体衬底可以从晶片分离。 还公开了处理系统和工艺中半导体晶片。