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    ECC METHOD FOR DOUBLE PATTERN FLASH MEMORY
    71.
    发明申请
    ECC METHOD FOR DOUBLE PATTERN FLASH MEMORY 有权

    公开(公告)号：US20150100852A1

    公开(公告)日：2015-04-09

    申请号：US14047418

    申请日：2013-10-07

    Applicant: Macronix International Co., Ltd.

    Inventor： Shih-Chang Huang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

    Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

    METHOD AND APPARATUS FOR REDUCING ERASE DISTURB OF MEMORY BY USING RECOVERY BIAS
    72.
    发明申请
    METHOD AND APPARATUS FOR REDUCING ERASE DISTURB OF MEMORY BY USING RECOVERY BIAS 审中-公开
    通过使用恢复偏差来减少存储器的擦除干扰的方法和装置

    公开(公告)号：US20150055412A1

    公开(公告)日：2015-02-26

    申请号：US14532610

    申请日：2014-11-04

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Lung Chang ,  Ken-Hui Chen

    IPC: G11C16/34

    CPC classification number: G11C16/3431 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/344

    Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

    Abstract translation: 非易失性存储器阵列被分成多个存储器组。 非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。 控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。 通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

    Self-calibration of output buffer driving strength
    73.
    发明授权
    Self-calibration of output buffer driving strength 有权

    公开(公告)号：US08847635B2

    公开(公告)日：2014-09-30

    申请号：US14158033

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H03K3/00

    CPC classification number: H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

    METHOD AND APPARATUS FOR THE ERASE SUSPEND OPERATION
    75.
    发明申请
    METHOD AND APPARATUS FOR THE ERASE SUSPEND OPERATION 有权
    擦除操作的方法和装置

    公开(公告)号：US20130294173A1

    公开(公告)日：2013-11-07

    申请号：US13936620

    申请日：2013-07-08

    Applicant: Macronix International Co., Ltd.

    Inventor： Chuan-Ying Yu ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Kuen-Long Chang

    IPC: G11C16/16

    CPC classification number: G11C16/16 ,  G11C16/345 ,  G11C16/3454

    Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

    Abstract translation: 非易失性存储器的各个方面具有改进的擦除暂停过程。 偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。 结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

    MANAGING STATUS OUTPUT
    79.
    发明公开
    MANAGING STATUS OUTPUT 审中-公开

    公开(公告)号：US20240184668A1

    公开(公告)日：2024-06-06

    申请号：US18191401

    申请日：2023-03-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Jung Chen ,  Ken-Hui Chen

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: Systems, devices, methods, and circuits for managing status output are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to execute a read operation in the memory array and output a read packet based on a result of the execution of the read operation. The read packet includes readout data and error information associated with the readout data. The error information is indicated by at least one of an error code or one or more secure codes in the read packet.

    MEMORY DEVICE
    80.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240170076A1

    公开(公告)日：2024-05-23

    申请号：US17988773

    申请日：2022-11-17

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Chen-Huan Chen ,  Ken-Hui Chen

    IPC: G11C16/34 ,  G11C7/10 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C16/08 ,  G11C16/24

    Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

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