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    SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES
    72.
    发明申请
    SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES 有权
    基板带隙工程多栅极PMOS器件

    公开(公告)号：US20100193840A1

    公开(公告)日：2010-08-05

    申请号：US12757917

    申请日：2010-04-09

    申请人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta

    发明人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta

    IPC分类号： H01L27/088

    CPC分类号： H01L29/78687 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78609

    摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.

    摘要翻译： 多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。 所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。 多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

    Transistor having tensile strained channel and system including same
    74.
    发明授权
    Transistor having tensile strained channel and system including same 有权
    具有拉伸应变通道的晶体管和包括其的系统

    公开(公告)号：US07569869B2

    公开(公告)日：2009-08-04

    申请号：US11729564

    申请日：2007-03-29

    申请人： Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

    发明人： Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

    IPC分类号： H01L29/737 ,  H01L29/778

    CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7843 ,  H01L29/7851

    摘要： A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

    摘要翻译： 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。

    INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS
    75.
    发明申请
    INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS 有权
    独立的N-TIPS多门控晶体管

    公开(公告)号：US20090140341A1

    公开(公告)日：2009-06-04

    申请号：US11948414

    申请日：2007-11-30

    申请人： Ravi Pillarisetty ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle

    发明人： Ravi Pillarisetty ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  H01L29/785

    摘要： Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.

    摘要翻译： 通常描述多栅极晶体管的独立n尖端。 在一个示例中，设备包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）器件，所述一个或多个PD器件在与半导体鳍片材料相邻的半导体鳍片材料中具有n端掺杂剂浓度 一个或多个PD器件，以及与半导体鳍片耦合的一个或多个多栅极通过栅极（PG）器件，所述一个或多个PG器件在与所述一个或多个PG相邻的半导体鳍片材料中具有n尖端掺杂剂浓度 器件，其中PG器件的n尖掺杂剂浓度低于PD器件的n尖掺杂剂浓度。

    SRAM and logic transistors with variable height multi-gate transistor architecture
    79.
    发明申请
    SRAM and logic transistors with variable height multi-gate transistor architecture 审中-公开
    具有可变高度多栅极晶体管结构的SRAM和逻辑晶体管

    公开(公告)号：US20080157225A1

    公开(公告)日：2008-07-03

    申请号：US11648521

    申请日：2006-12-29

    申请人： Suman Datta ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Yih Wang

    发明人： Suman Datta ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Yih Wang

    IPC分类号： H01L21/336 ,  H01L29/768

    CPC分类号： H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/66795 ,  H01L29/7851

    摘要： Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.

    摘要翻译： 形成在非平面半导体主体上的具有不同沟道宽度的多栅极晶体管具有不同的侧壁高度及其制造方法。 在一个实施例中，多栅极SRAM晶体管形成在具有比用于多栅极逻辑晶体管的非平面半导体主体更大的侧壁高度的非平面半导体主体上，以改善在栅极上形成的SRAM和逻辑晶体管的性能 相同的底物。 在另一个实施例中，为了减小单元面积，第一SRAM晶体管形成在具有比用于第二多栅极SRAM晶体管的非平面半导体主体更大的侧壁高度的非平面半导体本体上。