公开(公告)号：US20070293027A1

公开(公告)日：2007-12-20

申请号：US11687315

申请日：2007-03-16

申请人： Takuya Konno ,  Ichiro Mizushima ,  Takashi Suzuki ,  Nobuaki Makino

发明人： Takuya Konno ,  Ichiro Mizushima ,  Takashi Suzuki ,  Nobuaki Makino

IPC分类号： H01L21/223

CPC分类号： H01L21/223

摘要： A dopant diffusion method includes: diffusing a dopant element into a semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr. A temperature of the semiconductor is set less than 750° C. and not more than 950° C. A method of manufacturing a semiconductor device including a semiconductor with a dopant element diffused therein, the method includes: diffusing a dopant element into the semiconductor through an oxide film. The dopant element is contained in a compound gas having a gas partial pressure of not less than 0.1 torr and not more than 800 torr, and a temperature of the semiconductor is set less than 750° C. and not more than 950° C.

摘要翻译： 掺杂剂扩散方法包括：通过氧化物膜将掺杂剂元素扩散到半导体中。 掺杂剂元素包含在气体分压不小于0.1托且不大于800托的复合气体中。 半导体的温度设定为小于750℃且不高于950℃。一种制造半导体器件的方法，该半导体器件包括其中扩散掺杂剂元素的半导体，该方法包括：将掺杂元素扩散到半导体中，通过 氧化膜。 掺杂剂元素含有气体分压为0.1托以上800托以下的复合气体，半导体的温度设定为小于750℃，不高于950℃。

公开(公告)号：US07265017B2

公开(公告)日：2007-09-04

申请号：US11168914

申请日：2005-06-29

申请人： Hajime Nagano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Ichiro Mizushima

IPC分类号： H01L21/331

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

摘要翻译： 封闭半导体器件，其包括半导体衬底，该半导体衬底包括掩埋有第一绝缘膜的SOI区域和非SOI区域，该半导体衬底设置有形成在SOI区域与非SOI区域之间的边界区域 并且具有埋置在其中的第二绝缘膜，所述第二绝缘膜从所述SOI区域侧向非SOI区域侧向上倾斜，所述第二绝缘膜的厚度小于所述第一绝缘膜的厚度， SOI区域侧，分离地形成在半导体衬底的非SOI区域中并限定元件区域的一对元件隔离绝缘区域，形成在元件区域中的一对杂质扩散区域以及栅极电极 通过半导体衬底的元件区域中的栅极绝缘膜形成。

公开(公告)号：US07160818B2

公开(公告)日：2007-01-09

申请号：US11020271

申请日：2004-12-27

申请人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

发明人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

IPC分类号： H01L21/469 ,  H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： An aspect of the present invention includes; a silicon oxynitride film having an oxynitride layer which is formed on at least the surface of a silicon substrate and in which nitrogen atoms are in a three-coordinate bond state, and a silicon oxide layer which is formed between said oxynitride layer and said silicon substrate.

摘要翻译： 本发明的一个方面包括： 一种氧氮化硅膜，其形成在至少在硅衬底的表面上并且其中氮原子处于三坐标结合状态的氧氮化物层和形成在所述氧氮化物层和所述硅衬底之间的氧化硅层 。

公开(公告)号：US20060076624A1

公开(公告)日：2006-04-13

申请号：US11282784

申请日：2005-11-18

申请人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/76251 ,  H01L21/84

摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.

摘要翻译： 公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层， 不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面 层位于绝缘体上。

公开(公告)号：US06989316B2

公开(公告)日：2006-01-24

申请号：US10406281

申请日：2003-04-04

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L21/20

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

公开(公告)号：US06982198B2

公开(公告)日：2006-01-03

申请号：US11068853

申请日：2005-03-02

申请人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

发明人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

IPC分类号： H01L21/8242

CPC分类号： H01L21/76847 ,  H01L21/76864 ,  H01L27/10867 ,  H01L29/945

摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体衬底或沉积在所述半导体衬底上的层中的沟槽; 沉积在所述沟槽中并在其顶表面中具有凹部的第一导电层; 掩埋层，其埋入第一导电层的凹部，并且由熔点低于第一导电层的熔点的材料制成; 以及形成在所述沟槽内的所述掩埋层上并电连接到所述第一导电层的第二导电层。

公开(公告)号：US20050170582A1

公开(公告)日：2005-08-04

申请号：US11068848

申请日：2005-03-02

申请人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

发明人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L31/119

CPC分类号： H01L21/76847 ,  H01L21/76864 ,  H01L27/10867 ,  H01L29/945

摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

公开(公告)号：US20050167720A1

公开(公告)日：2005-08-04

申请号：US11068853

申请日：2005-03-02

申请人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

发明人： Takeo Furuhata ,  Ichiro Mizushima ,  Akiko Sekihara ,  Motoya Kishida ,  Tsubasa Harada ,  Takashi Nakao

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L31/119

CPC分类号： H01L21/76847 ,  H01L21/76864 ,  H01L27/10867 ,  H01L29/945

摘要： A semiconductor device comprises a semiconductor substrate; a trench formed in the semiconductor substrate or in a layer deposited on the semiconductor substrate; a first conductive layer deposited in the trench and having a recess in the top surface thereof; a buried layer which buries the recess of the first conductive layer and which is made of a material having a melting point lower than that of the first conductive layer; and a second conductive layer formed on the buried layer inside the trench and electrically connected to the first conductive layer.

公开(公告)号：US06906384B2

公开(公告)日：2005-06-14

申请号：US10096655

申请日：2002-03-14

申请人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

发明人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/10861 ,  H01L21/76243 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78639

摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

摘要翻译： 半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。 第一半导体层设置在半导体衬底上并与之电连接。 第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。 第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

公开(公告)号：US06846750B1

公开(公告)日：2005-01-25

申请号：US09604724

申请日：2000-06-28

申请人： Tokuhisa Ohiwa ,  Shoji Seta ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Akihiro Kojima ,  Junko Ohuchi ,  Tsukasa Azuma ,  Hideo Ichinose ,  Ichiro Mizushima

发明人： Tokuhisa Ohiwa ,  Shoji Seta ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Akihiro Kojima ,  Junko Ohuchi ,  Tsukasa Azuma ,  Hideo Ichinose ,  Ichiro Mizushima

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/30 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/461

CPC分类号： H01L21/76802 ,  H01L21/0331 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/76816 ,  H01L21/7682

摘要： According to the present invention, there is provided a method of manufacturing a semiconductor device, where a soluble thin film which is soluble in a dissolving liquid is used. According to the method of the present invention, when a soluble thin film is formed between a film to be processed which should be patterned and a mask pattern, it becomes possible to remove the mask pattern by lifting-off. On the other hand, when the thin film is used for a dummy layer for forming an air wiring structure, the dummy layer can be removed without performing ashing using oxygen plasma.

摘要翻译： 根据本发明，提供一种制造半导体器件的方法，其中使用可溶于溶解液的可溶性薄膜。 根据本发明的方法，当在要被图案化的被处理膜和掩模图案之间形成可溶性薄膜时，可以通过剥离来去除掩模图案。 另一方面，当薄膜用于形成空气布线结构的虚拟层时，可以去除虚拟层而不用氧等离子体进行灰化。