公开(公告)号：US06603204B2

公开(公告)日：2003-08-05

申请号：US09795431

申请日：2001-02-28

申请人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

发明人： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

IPC分类号： H01L2348

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：US09105693B2

公开(公告)日：2015-08-11

申请号：US13614563

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/40 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。

公开(公告)号：US20130175697A1

公开(公告)日：2013-07-11

申请号：US13344009

申请日：2012-01-05

申请人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Satyanarayana V. Nitta

发明人： Son Van Nguyen ,  Griselda Bonilla ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Satyanarayana V. Nitta

IPC分类号： H01L23/538 ,  H01L21/31 ,  B32B9/04

CPC分类号： H01L23/5384 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/249969 ,  H01L2924/00

摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

摘要翻译： 一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。 电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。 该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。 电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分 。

公开(公告)号：US08338952B2

公开(公告)日：2012-12-25

申请号：US12538114

申请日：2009-08-08

申请人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

发明人： Matthew E. Colburn ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman

IPC分类号： H01L21/70 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low k and high structural integrity. The method includes depositing an interlayer dielectric onto the semiconductor substrate, forming a first pattern within the interlayer dielectric material by a first lithographic process that results in both via features and ternary features being formed in the interconnect structure. The method further includes forming a second pattern within the interlayer dielectric material by a second lithographic process to form line features within the interconnect structure. Hence the method forms the three separate distinct patterned structures using only two lithographic processes for each interconnect level.

摘要翻译： 一种制造互连结构的方法，用于将半导体衬底互连以具有三个不同的图案化结构，使得互连结构既提供低k和高结构完整性。 该方法包括在半导体衬底上沉积层间电介质，通过第一光刻工艺在层间电介质材料内形成第一图案，该第一光刻工艺导致在互连结构中形成通孔特征和三元特征。 该方法还包括通过第二光刻工艺在层间电介质材料内形成第二图案以在互连结构内形成线特征。 因此，该方法仅对每个互连级别仅使用两个光刻工艺形成三个独立的不同图案结构。

公开(公告)号：US20120306018A1

公开(公告)日：2012-12-06

申请号：US13149797

申请日：2011-05-31

申请人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

发明人： Stephen M. Gates ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta

IPC分类号： H01L29/772 ,  H01L29/92 ,  H01L21/20 ,  H01L29/02

CPC分类号： H01L23/481 ,  H01L21/02667 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L27/016 ,  H01L27/0688 ,  H01L29/66984 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00

摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

摘要翻译： 单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。 半导体器件层没有与衬底接合或结合界面。 使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层 形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层 通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

公开(公告)号：US08120179B2

公开(公告)日：2012-02-21

申请号：US12615354

申请日：2009-11-10

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US20120038056A1

公开(公告)日：2012-02-16

申请号：US12853537

申请日：2010-08-10

申请人： Cyril Cabral, JR. ,  Sebastian U. Engelmann ,  Benjamin Fletcher ,  Eric A. Joseph ,  Satyanarayana V. Nitta

发明人： Cyril Cabral, JR. ,  Sebastian U. Engelmann ,  Benjamin Fletcher ,  Eric A. Joseph ,  Satyanarayana V. Nitta

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L21/76816 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

摘要翻译： 本公开提供了形成到电气设备的互连的方法。 在一个实施例中，形成互连的方法包括在衬底上提供器件层，其中所述器件层包括至少一个电器件，在所述至少一个电器件上的入口电介质，以及与所述至少一个电器件电连接的触点 所述至少一个电气设备。 在器件层上形成互连金属层，并且在互连金属层的一部分上形成含钽蚀刻掩模。 蚀刻互连金属层以提供与至少一个电气设备连通的梯形互连。 梯形互连具有与器件层接触的第一表面，其具有比与含钽蚀刻掩模接触的梯形互连的第二表面更大的宽度。

公开(公告)号：US20110227232A1

公开(公告)日：2011-09-22

申请号：US12724903

申请日：2010-03-16

申请人： Griselda Bonilla ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming crenulated conductors and a device having crenulated conductors includes forming a hardmask layer on a dielectric layer, and patterning the hardmask layer. Trenches are etched in the dielectric layer using the hardmask layer such that the trenches have shallower portions and deeper portions alternating along a length of the trench. A conductor is deposited in the trenches such that crenulated conductive lines are formed having different depths periodically disposed along the length of the conductive line.

摘要翻译： 用于形成齿形导体的方法和具有齿形导体的器件包括在介电层上形成硬掩模层，并对硬掩模层进行构图。 使用硬掩模层在电介质层中蚀刻沟槽，使得沟槽具有沿着沟槽的长度交替的较浅部分和较深部分。 导体沉积在沟槽中，使得形成具有沿着导电线的长度周期性地设置的不同深度的锯齿形导电线。

公开(公告)号：US07943480B2

公开(公告)日：2011-05-17

申请号：US12029800

申请日：2008-02-12

申请人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

发明人： Daniel C. Edelstein ,  Nicholas C. M. Fuller ,  David V. Horak ,  Elbert E. Huang ,  Wai-Kin Li ,  Anthony D. Lisi ,  Satyanarayana V. Nitta ,  Shom Ponoth

IPC分类号： H01L23/00

CPC分类号： H01L21/7682 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

摘要翻译： 公开了亚光刻尺寸气隙形成和相关结构。 在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

公开(公告)号：US20100285667A1

公开(公告)日：2010-11-11

申请号：US12436459

申请日：2009-05-06

申请人： Griselda Bonilla ,  Satyanarayana V. Nitta ,  Terry A. Spooner

发明人： Griselda Bonilla ,  Satyanarayana V. Nitta ,  Terry A. Spooner

IPC分类号： H01L21/302

CPC分类号： H01L21/3105 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material.

摘要翻译： 提供了一种在通过湿蚀刻化学去除损伤层之前，在低k电介质材料的干蚀刻期间恢复低k电介质材料的暴露表面的介电常数，损耗和泄漏的方法。 一旦恢复，电介质材料的表面将不再易于被高度各向异性的湿法蚀刻工艺去除。 然而，湿式蚀刻仍将具有优势，因为它可以去除形成在低k电介质材料中的特征底部的任何蚀刻/灰渣。