公开(公告)号：US09041144B2

公开(公告)日：2015-05-26

申请号：US13897047

申请日：2013-05-17

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088 ,  H01L27/085 ,  H01L27/06 ,  H01L27/115

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract translation: 一些实施例包括具有第一和第二晶体管的集成电路。 第一晶体管比第二晶体管宽。 第一和第二晶体管分别具有第一和第二有源区。 电介质特征与第一有源区相关联并且分解第一有源区。 第二活性区域不会分解成与第一活性区域相同的程度。 一些实施例包括形成晶体管的方法。 形成第一和第二晶体管的有源区。 第一晶体管的有效面积比第二晶体管的有效面积宽。 电介质特征形成在第一晶体管的有源区中。 第一晶体管的有效面积被分解为与第二晶体管的有效面积不同的程度。 第一和第二晶体管的有源区同时掺杂。

公开(公告)号：US20240428859A1

公开(公告)日：2024-12-26

申请号：US18830525

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/08 ,  G11C16/04 ,  H01L29/10 ,  H01L29/78

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US20240322049A1

公开(公告)日：2024-09-26

申请号：US18588352

申请日：2024-02-27

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Haitao Liu ,  Michael A. Smith

IPC: H01L29/861 ,  H01L21/265 ,  H01L21/768 ,  H01L23/00 ,  H01L29/66 ,  H10B80/00

CPC classification number: H01L29/861 ,  H01L21/265 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/80 ,  H01L29/6609 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor device including a first semiconductor device that includes a substrate, a memory array disposed above the substrate and below a frontside surface of the first semiconductor device, a plurality of source region contact (SRC) nodes disposed under the memory array, and a plurality of high-voltage (HV) diodes disposed in the substrate, each of the plurality of HV diodes being connected to corresponding one of the plurality of SRC nodes; and a second semiconductor device including a plurality of complementary-metal-oxide semiconductor (CMOS) devices, each of the plurality of CMOS devices being connected to, through a backside surface of the second semiconductor device and the frontside surface of the first semiconductor device, corresponding bond pad of the memory array, wherein fusion bonding exists between the backside surface of the second semiconductor device and the frontside surface of the first semiconductor device.

公开(公告)号：US20240274533A1

公开(公告)日：2024-08-15

申请号：US18416227

申请日：2024-01-18

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp ,  Richard J. Hill

IPC: H01L23/528 ,  G11C5/06 ,  G11C16/04 ,  H01L21/762 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C16/0483 ,  H01L21/76224 ,  H01L25/0657 ,  H01L27/0922 ,  H01L29/0649 ,  H01L2225/06524

Abstract: A semiconductor device assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver, wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.

公开(公告)号：US20230395151A1

公开(公告)日：2023-12-07

申请号：US18237070

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  H01L29/7833 ,  H01L29/1083 ,  G11C16/0483

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US20230387258A1

公开(公告)日：2023-11-30

申请号：US17752610

申请日：2022-05-24

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/6659 ,  H01L29/7833 ,  H01L29/404 ,  H01L29/42356

Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor can include a gate disposed between a source area and a drain area of the transistor. The transistor can also include a plurality of routing lanes above the gate for use by automated routing programs that layout metal connections for the apparatus. A first field plate can be disposed above a LDD region of the source area with the first field plate being on a same level as the plurality of routing lanes. A second field plate can be disposed above a LDD region of the drain area with the second field plate being on the same level as the plurality of routing lanes. The first and second field plates can be electrically connected to the gate using respective first and second path that bypass the plurality of routing lanes.

公开(公告)号：US11823731B2

公开(公告)日：2023-11-21

申请号：US17448976

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Kenneth W. Marr ,  Michael A. Smith

IPC: G11C8/20 ,  G11C11/4078 ,  G11C16/22 ,  G11C16/04 ,  G11C7/24 ,  G11C11/22 ,  G11C11/16

CPC classification number: G11C11/4078 ,  G11C7/24 ,  G11C8/20 ,  G11C11/1695 ,  G11C11/2295 ,  G11C16/0483 ,  G11C16/22

Abstract: Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

公开(公告)号：US20230275042A1

公开(公告)日：2023-08-31

申请号：US18142992

申请日：2023-05-03

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L23/60 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/60 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

公开(公告)号：US20230110692A1

公开(公告)日：2023-04-13

申请号：US18079848

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L21/266

Abstract: An apparatus includes a substrate and a transistor disposed on the substrate. The transistor includes a source and a source contact disposed on the source. The transistor also includes a drain and a drain contact disposed on the drain. A gate is disposed between the source contact and the drain contact, and a screened region is disposed adjacent the source contact or the drain contact. The screened region corresponds to a lightly doped region. The screened region includes an implant screen configured to reduce an effective dose in the screened region so as to shift an acceptable dose range of the screened region to a higher dose range. The acceptable dose range corresponds to acceptable breakdown voltage values for the screened region.

公开(公告)号：US11557537B2

公开(公告)日：2023-01-17

申请号：US16986776

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/11 ,  H01L29/66

Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.