公开(公告)号：US07666788B2

公开(公告)日：2010-02-23

申请号：US11717437

申请日：2007-03-12

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.

摘要翻译： 在半导体器件部件的衬底中形成导电通孔的方法包括在衬底中形成一个或多个孔或孔或空腔，以便仅部分延伸穿过衬底。 可以在每个孔的表面上形成诸如绝缘层的阻挡层。 每个孔中的表面可以涂覆有种子层，这有助于在每个孔内粘附导电材料。 将导电材料引入每个孔中。 导电材料的引入可以通过沉积或电镀来实现。 或者，可以将每种孔中引入焊料形式的导电材料。

公开(公告)号：US20090211595A1

公开(公告)日：2009-08-27

申请号：US12035008

申请日：2008-02-21

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： B08B7/00 ,  H01L21/00 ,  C25B9/00

CPC分类号： H01L21/67057 ,  B08B3/04 ,  B08B7/00 ,  H01L21/67086 ,  Y10T137/206 ,  Y10T428/24521

摘要： Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided.

摘要翻译： 提供了使用电粘滞性（ER）和磁流变（MR）流体制造半导体器件中的衬底（例如，晶片）以从衬底表面去除污染物残留颗粒的方法和装置。

公开(公告)号：US20090114246A1

公开(公告)日：2009-05-07

申请号：US11933770

申请日：2007-11-01

申请人： Nishant Sinha ,  Gurtej S. Sandhu

发明人： Nishant Sinha ,  Gurtej S. Sandhu

IPC分类号： B08B6/00 ,  B08B3/00

CPC分类号： B08B3/10 ,  B08B7/02 ,  B24C3/322 ,  B24C7/0007 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67051

摘要： Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer layer may be formed across a surface. The dispersion may be directed toward the transfer layer, and the insolubles may impact the transfer layer. The impacting may generate force in the transfer layer, and such force may be transferred through the transfer layer to the surface. The surface may be a surface of a semiconductor substrate, and the force may be utilized to sweep contaminants from the semiconductor substrate surface. The transfer layer may be a liquid, and in some embodiments may be a cleaning solution.

摘要翻译： 一些实施方案包括用于处理表面的方法。 珠和/或其他不溶物可以分散在液体载体中以形成分散体。 可以跨越表面形成转印层。 分散体可以指向转移层，并且不溶物可能影响转移层。 冲击可能在转移层中产生力，并且这种力可以通过转移层转移到表面。 表面可以是半导体衬底的表面，并且该力可用于从半导体衬底表面扫除污染物。 转移层可以是液体，并且在一些实施方案中可以是清洁溶液。

公开(公告)号：US20070170595A1

公开(公告)日：2007-07-26

申请号：US11717294

申请日：2007-03-12

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a conductive material within the via aperture, a barrier material and solder, or a silicon-containing filler. Systems including such semiconductor device components are also disclosed.

摘要翻译： 半导体器件部件包括至少一个导电通孔。 至少一个导电通孔可以包括种子层，用于促进导电材料在通孔孔内的粘附，阻挡材料和焊料，或含硅填料。 还公开了包括这种半导体器件部件的系统。

公开(公告)号：US20070169343A1

公开(公告)日：2007-07-26

申请号：US11717946

申请日：2007-03-13

申请人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

发明人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

IPC分类号： H05K3/02 ,  H01R9/00

CPC分类号： H05K3/426 ,  H01L21/486 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/4916 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

摘要： Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.

摘要翻译： 衬底前体结构包括具有基本上延伸穿过衬底坯料的至少一个孔的衬底坯料。 至少一个导电层的至少一部分覆盖衬底坯料的至少一个孔的表面。 掩模图案覆盖所述至少一个导电层的一部分并且暴露所述至少一个导电层的另一部分以限定至少一个导电元件，其至少一部分在所述至少一个孔的表面上延伸。

公开(公告)号：US20070166991A1

公开(公告)日：2007-07-19

申请号：US11717437

申请日：2007-03-12

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.

摘要翻译： 在半导体器件部件的衬底中形成导电通孔的方法包括在衬底中形成一个或多个孔或孔或空腔，以便仅部分延伸穿过衬底。 可以在每个孔的表面上形成诸如绝缘层的阻挡层。 每个孔中的表面可以涂覆有种子层，这有助于在每个孔内粘附导电材料。 将导电材料引入每个孔中。 导电材料的引入可以通过沉积或电镀来实现。 或者，可以将每种孔中引入焊料形式的导电材料。

公开(公告)号：US07183133B2

公开(公告)日：2007-02-27

申请号：US10767232

申请日：2004-01-28

申请人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

发明人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

IPC分类号： H01L21/44

CPC分类号： H01L23/367 ,  H01L23/427 ,  H01L24/31 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2224/0401

摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

摘要翻译： 本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。 在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。 第二表面具有增加第二表面的表面积的多个传热表面特征。 在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

公开(公告)号：US20070032069A1

公开(公告)日：2007-02-08

申请号：US11198208

申请日：2005-08-05

申请人： Paul Morgan ,  Nishant Sinha

发明人： Paul Morgan ,  Nishant Sinha

IPC分类号： H01L21/4763

CPC分类号： H01L21/283 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76879

摘要： Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer.

摘要翻译： 提供了以最小化或消除钥匙孔形成的方式在电介质层上选择性沉积金属。 根据一个实施例，介电目标层形成在衬底层上，其中目标层可以被配置为允许保形金属沉积，并且在目标层上形成介电第二层，其中第二层可以被配置为允许 自下而上的金属沉积。 然后可以在第二层中形成开口，并且可以在衬底层上选择性地沉积金属。

公开(公告)号：US07122420B2

公开(公告)日：2006-10-17

申请号：US11064982

申请日：2005-02-23

申请人： Theodore M. Taylor ,  Nishant Sinha

发明人： Theodore M. Taylor ,  Nishant Sinha

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L27/10808 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855

摘要： The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a semiconductor substrate. The construction also includes openings extending through the first electrically conductive material and into the semiconductor substrate. A second electrically conductive material is formed within the openings and over the first electrically conductive material and is in electrical contact with the first electrically conductive material. The second electrically conductive material is subjected to anodic dissolution while the first electrically conductive material is electrically connected to a power source. The second electrically conductive material within the openings becomes electrically isolated from the first electrically conductive material as the dissolution progresses, and some of the second electrically conductive material remains within the openings in the substrate as spaced conductive regions after the anodic dissolution.

摘要翻译： 本发明包括形成间隔导电区域的方法。 形成包括半导体衬底上的第一导电材料的结构。 该结构还包括延伸穿过第一导电材料并进入半导体衬底的开口。 第二导电材料形成在开口内并且在第一导电材料之上并且与第一导电材料电接触。 当第一导电材料电连接到电源时，第二导电材料经受阳极溶解。 当溶解进行时，开口内的第二导电材料与第一导电材料电绝缘，并且一些第二导电材料在阳极溶解后作为间隔的导电区域留在衬底的开口内。

公开(公告)号：US07005379B2

公开(公告)日：2006-02-28

申请号：US10822030

申请日：2004-04-08

申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

IPC分类号： H01L21/44 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。