公开(公告)号：US20080157162A1

公开(公告)日：2008-07-03

申请号：US11646757

申请日：2006-12-27

申请人： Brian S. Doyle ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

发明人： Brian S. Doyle ,  Suman Datta ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7841 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/1203

摘要： An integrated circuit having both floating body cells and logic devices fabricated in a bulk silicon substrate is described. The floating body cells have electrically floating bodies formed by oxidizing a lower portion of the cell bodies to electrically isolate them from the substrate.

摘要翻译： 描述了具有在体硅衬底中制造的浮体单元和逻辑器件的集成电路。 浮体电池具有通过氧化电池体的下部而与衬底电隔离而形成的电浮体。

公开(公告)号：US07368791B2

公开(公告)日：2008-05-06

申请号：US11215559

申请日：2005-08-29

申请人： Yuegang Zhang ,  Brian S. Doyle ,  George I. Bourianoff

发明人： Yuegang Zhang ,  Brian S. Doyle ,  George I. Bourianoff

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： According to one aspect of the invention, a semiconducting transistor is described. The channel portion of the transistor includes carbon nanotubes formed on top of an insulating layer which covers a local bottom gate. Source and drain conductors are located at ends of the carbon nanotubes. A gate dielectric surrounds a portion of the carbon nanotubes with a substantially uniform thickness. A local top gate is located between the source and drain conductors over the carbon nanotubes. Lower portions of the local top gate are positioned between the carbon nanotubes as the local top gate forms pi-gates or “wraparound” gates around each carbon nanotube.

摘要翻译： 根据本发明的一个方面，描述了半导体晶体管。 晶体管的沟道部分包括形成在覆盖局部底栅的绝缘层的顶部上的碳纳米管。 源极和漏极导体位于碳纳米管的端部。 栅极电介质以基本均匀的厚度围绕碳纳米管的一部分。 局部顶栅位于碳纳米管之间的源极和漏极导体之间​​。 局部顶栅的下部位于碳纳米管之间，因为局部顶栅在每个碳纳米管周围形成边界或“环绕”门。

公开(公告)号：US07358121B2

公开(公告)日：2008-04-15

申请号：US10227068

申请日：2002-08-23

申请人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta

发明人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

公开(公告)号：US07223992B2

公开(公告)日：2007-05-29

申请号：US11331321

申请日：2006-01-11

申请人： Chunlin Liang ,  Brian S. Doyle

发明人： Chunlin Liang ,  Brian S. Doyle

IPC分类号： H01L47/00 ,  H01L29/148

CPC分类号： H01L21/76801 ,  H01L21/76224 ,  H01L21/763 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： The invention relates to a trench filled with a thermally conducting material in a semiconductor substrate. In one embodiment, the semiconductor device has a trench defining a cell region, wherein a portion of the trench includes a thermally conducting material, and a contact to the thermally conducting material. The invention further relates to a semiconductor device and a method of forming a semiconductor device with an interlayer dielectric that is a thermally conducting material.

摘要翻译： 本发明涉及在半导体衬底中填充有导热材料的沟槽。 在一个实施例中，半导体器件具有限定单元区域的沟槽，其中沟槽的一部分包括导热材料和与导热材料的接触。 本发明还涉及半导体器件和形成具有作为导热材料的层间电介质的半导体器件的方法。

公开(公告)号：US07138316B2

公开(公告)日：2006-11-21

申请号：US10669064

申请日：2003-09-23

申请人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US06998357B2

公开(公告)日：2006-02-14

申请号：US10646034

申请日：2003-08-22

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L21/469

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

公开(公告)号：US06972228B2

公开(公告)日：2005-12-06

申请号：US10387623

申请日：2003-03-12

申请人： Brian S. Doyle ,  Anand S. Murthy ,  Robert S. Chau

发明人： Brian S. Doyle ,  Anand S. Murthy ,  Robert S. Chau

IPC分类号： H01L21/20 ,  H01L29/12 ,  H01S5/34 ,  H01L21/8242

CPC分类号： H01L29/66795 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L29/125 ,  H01S5/341

摘要： A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

摘要翻译： 描述了形成微电子电路的元件的方法。 牺牲层形成在支撑层的上表面上。 牺牲层非常薄而均匀。 然后在牺牲层上形成高度限定层，然后牺牲层被蚀刻掉，使得在支撑层的上表面和高度限定层的下表面之间留下明确限定的间隙。 然后从成核硅部位通过间隙选择性地生长单晶半导体材料。 单晶半导体材料形成具有对应于原始牺牲层的厚度的厚度的单晶层。

公开(公告)号：US06960517B2

公开(公告)日：2005-11-01

申请号：US10610835

申请日：2003-06-30

申请人： Rafael Rios ,  Brian S. Doyle ,  Thomas D. Linton, Jr. ,  Jack Kavalieros

发明人： Rafael Rios ,  Brian S. Doyle ,  Thomas D. Linton, Jr. ,  Jack Kavalieros

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/3205

CPC分类号： H01L29/7853 ,  H01L29/66795

摘要： A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.

摘要翻译： 一种n型栅极晶体管及其形成方法，包括由沟道区域连接的源极/漏极区域和耦合到沟道区域的栅电极。 通道区域具有突出到栅电极中的许多成角度的边缘。 许多成角度的边缘用作在源极/漏极区域之间的导电沟道导管。

公开(公告)号：US06887395B2

公开(公告)日：2005-05-03

申请号：US10364281

申请日：2003-02-10

申请人： Scott A. Hareland ,  Brian S. Doyle ,  Robert S. Chau

发明人： Scott A. Hareland ,  Brian S. Doyle ,  Robert S. Chau

IPC分类号： B44C1/22 ,  B81B1/00 ,  B81C1/00 ,  H01L21/00 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0673 ,  Y10S438/947

摘要： A method is provided for forming sub-micron-size structures over a substrate. A width-defining step is formed over the substrate. A width-defining layer is formed over an edge of the width-defining step. The width-defining layer is etched back to leave a spacer adjacent the width-defining step. A length-defining step is formed over the substrate. A length-defining layer is formed over an edge of the length-defining step. The length-defining layer is etched back to leave a spacer adjacent a first edge of the length-defining step and across a first portion of the spacer left by the width-defining layer. The length-defining step is then removed. The spacer left by the width-defining layer is then etched with the spacer left by the length-defining layer serving as a mask, to form the structure.

摘要翻译： 提供了一种在衬底上形成亚微米级结构的方法。 在衬底上形成宽度限定步骤。 宽度限定层形成在宽度限定步骤的边缘上。 将宽度限定层回蚀刻以在宽度限定步骤附近留下间隔物。 在衬底上形成长度限定步骤。 长度限定层形成在长度限定步骤的边缘上。 长度限定层被回蚀刻以在与长度限定步骤的第一边缘相邻并且横跨由宽度限定层留下的间隔物的第一部分附近留下间隔物。 然后去除长度定义步骤。 然后由宽度限定层留下的间隔物用作为掩模的长度限定层留下的间隔物进行蚀刻，以形成结构。

公开(公告)号：US06858478B2

公开(公告)日：2005-02-22

申请号：US10367263

申请日：2003-02-14

申请人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

发明人： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

摘要翻译： 本发明是一种半导体器件，其包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 栅极电极形成在半导体本体的顶表面上的栅电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。