公开(公告)号：US06396308B1

公开(公告)日：2002-05-28

申请号：US09795281

申请日：2001-02-27

申请人： Robert J. Bosnyak ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03F345

CPC分类号： G11C7/065 ,  G11C2207/005

摘要： A sense amplifier having dual differential inputs configured to accept differential analog input voltages. The differential analog input voltages are fused to determine a weighted signal digitally representative of the differential analog input voltages. An input offset voltage cancellation circuit may be coupled to the sense amplifier to reduce an input offset voltage of the sense amplifier.

摘要翻译： 具有双差分输入的读出放大器被配置为接受差分模拟输入电压。 差分模拟输入电压被融合以确定数字代表差分模拟输入电压的加权信号。 输入偏移电压消除电路可以耦合到读出放大器以减小读出放大器的输入偏移电压。

公开(公告)号：US6084452A

公开(公告)日：2000-07-04

申请号：US107898

申请日：1998-06-30

申请人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

IPC分类号： H03K5/156 ,  H03K3/017

CPC分类号： H03K5/1565

摘要： An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal. The duty cycle error measurement circuit rejects the common mode of the reference and comparison signals and passes the differential mode of the reference and comparison signals to generate a duty cycle adjust signal responsive to receiving the reference and comparison signals. The duty cycle adjuster is coupled to receive an input clock signal and the duty cycle adjust signal and to provide the single-ended clock signal. The single-ended clock signal has a duty cycle determined at least in part by the duty cycle adjust signal.

摘要翻译： 一个装置调整单端时钟信号的占空比。 单端时钟信号在第一和第二电压之间振荡。 该装置包括误差指示电路，占空比误差测量电路和占空比调节器。 误差指示电路包括参考电路和比较电路。 参考电路耦合到具有第一电压的第一节点和具有第二电压的第二节点以从第一和第二电压产生参考信号。 参考电路包括第一电特征单元的至少一个实例。 比较电路被耦合以接收反馈时钟信号并从其产生比较信号。 比较电路包括第一电特征单元的至少一个实例。 负载周期误差测量电路被耦合以接收参考信号和比较信号。 占空比误差测量电路拒绝参考和比较信号的共模，并通过参考和比较信号的差分模式，以响应于接收参考和比较信号产生占空比调整信号。 负载周期调节器被耦合以接收输入时钟信号和占空比调整信号并提供单端时钟信号。 单端时钟信号具有至少部分由占空比调整信号确定的占空比。

公开(公告)号：US6020765A

公开(公告)日：2000-02-01

申请号：US866653

申请日：1997-05-30

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03K5/26 ,  H03L7/085 ,  H03L7/087 ,  H04L7/033 ,  H04L25/40 ,  H03D13/00

CPC分类号： H03L7/085 ,  H04L7/033

摘要： A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal. It is also preferred that the error pulses have a repetition rate that corresponds to the edges of the NRZ signal, a current amplitude that is proportional to the frequency difference between the NRZ signal and the reference signal, and a polarity that represents a sign of the frequency difference between the NRZ signal and the reference signal. The frequency difference detector is well-suited for use in a frequency/phase-locked loop that provides a clock recovery circuit.

摘要翻译： 频率差检测器包括脉冲发生器，其接收NRZ信号和参考信号，并且基于参考信号的边缘提供基于NRZ信号和第二边缘的第一边缘的数据脉冲，脉冲路由器将连续的 数据脉冲到不同的信号路径，电压发生器，其从信号路径接收数据脉冲，并提供基于数据脉冲的脉冲宽度的幅度的电压信号;以及比较电路，其接收电压信号并提供具有幅度的误差脉冲 基于电压信号之间的电压差。 误差脉冲的振幅表示NRZ信号和参考信号之间的频率差。 优选地，数据脉冲具有基于NRZ信号的边缘的前沿，并且基于紧跟NRZ信号的边缘的参考信号的前沿之后的滞后边缘。 还优选地，误差脉冲具有对应于NRZ信号的边缘的重复率，与NRZ信号和参考信号之间的频率差成比例的电流幅度，以及表示该NRZ信号的符号的极性 NRZ信号与参考信号之间的频率差。 频率差检测器非常适用于提供时钟恢复电路的频率/锁相环。

公开(公告)号：US6016082A

公开(公告)日：2000-01-18

申请号：US23360

申请日：1998-02-13

申请人： Jose M. Cruz ,  Robert J. Bosnyak ,  Robert J. Drost

发明人： Jose M. Cruz ,  Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H03B1/00 ,  H03B5/12 ,  H03L7/093 ,  H03L7/099 ,  H03L7/183 ,  H03B5/18

CPC分类号： H03L7/183 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1271 ,  H03L7/093 ,  H03L7/099 ,  H03B2201/0208

摘要： A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit. Continuously modifiable gigahertz frequency VCO circuit generates an output signal with a frequency that is dependent on the voltage on control voltage input line. The output signal from the continuously modifiable gigahertz frequency VCO is a differential current signal to a level shifter output circuit. The level shifter output circuit converts the current signal to a single-ended voltage that is supplied to an output driver. The output driver provides the output signal to a clock distribution network.

摘要翻译： 微处理器包括片上低相位噪声CMOS LC电容振荡器。 LC振荡器对电源波动相对不敏​​感。 此外，LC振荡器可以在足以支持正常全功率操作和微处理器的功率操作的减少的频率范围内操作。 LC振荡器使时钟抖动问题最小化，因此允许将微处理器工作频率扩展到甚至比以前更高的水平。 来自相位频率检测器的输出信号是LC振荡器的电平转换器和滤波器电路的频率控制输入线上的频率控制信号。 来自电平转换器和滤波器电路的输出信号是在可连续修改的千兆赫兹频率压控振荡器（VCO）电路的控制电压输入线上的滤波频率控制信号。 连续可修改的千兆赫兹频率VCO电路产生的输出信号的频率取决于控制电压输入线上的电压。 来自连续可修改的千兆赫兹频率VCO的输出信号是到电平移位器输出电路的差分电流信号。 电平移位器输出电路将电流信号转换为提供给输出驱动器的单端电压。 输出驱动器将输出信号提供给时钟分配网络。

公开(公告)号：US5920215A

公开(公告)日：1999-07-06

申请号：US885048

申请日：1997-06-30

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0896

摘要： In a charge pump the noise due to switching transients on the input pulse lines is kept to extremely low levels by translating input up/down pulses into small signal differential pulses which swing a differential pair of transistors by a small amount. This is done with level converters. The differential pair is kept in a saturation region, so that a large swing is not needed from the level converters and channel creation/destruction noise is avoided in addition to the noise reduction due to smaller swings. To avoid inherent offsets which might require a nonzero delta time width difference in the input pulses to produce a zero delta current, identical differential structures are used at the inputs for the two input pulse signals.

摘要翻译： 在电荷泵中，通过将输入上/下脉冲转换成将差分晶体管对摆动少量的小信号差分脉冲，将输入脉冲线上的切换瞬变引起的噪声保持在极低的水平。 这是用电平转换器完成的。 差分对保持在饱和区域，使得除了由于较小的摆动引起的噪声降低之外，电平转换器不需要大的摆幅并且避免了信道产生/破坏噪声。 为了避免可能需要输入脉冲中的非零增量时间宽度差产生零增量电流的固有偏移，在两个输入脉冲信号的输入端使用相同的差分结构。

公开(公告)号：US5850163A

公开(公告)日：1998-12-15

申请号：US828245

申请日：1997-03-31

申请人： Robert J. Drost ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Robert J. Bosnyak

IPC分类号： H03B5/12 ,  H03H11/48 ,  H03L7/099 ,  H03B5/00

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1259 ,  H03B5/1271 ,  H03H11/48

摘要： An active inductor oscillator includes a tank circuit for generating a first differential signal, a common-mode inverting differential buffer for generating a second differential signal in response to the first differential signal, and an integrating circuit for generating a third differential signal in response to the second differential signal. The third differential signal is applied to the tank circuit, and lags the first differential signal. A differential transistor pair in the tank circuit provides active inductance in response to the third differential signal, and a cross-coupled transistor pair in the tank circuit provides negative resistance that amplifies the first differential signal in response to the first differential signal. Currents through the tank circuit, buffer, and integrating circuit are essentially identical to one another and move in unison with an externally applied reference current that controls the oscillation frequency. As a result, the oscillator can achieve a wide range of oscillation frequencies. The buffer adds 180 degrees of phase shift to the common-mode loop, thereby providing negative common-mode feedback that prevents lock-up. The tank circuit, buffer and integrating circuit use differential transistor pairs that reduce phase jitter due to external common-mode noise sources.

摘要翻译： 有源电感振荡器包括用于产生第一差分信号的振荡电路，用于响应于第一差分信号产生第二差分信号的共模反相差分缓冲器，以及用于响应于第一差分信号产生第三差分信号的积分电路 第二差分信号。 第三差分信号被施加到储能电路，并且滞后于第一差分信号。 储能电路中的差分晶体管对响应于第三差分信号提供有效电感，并且在谐振电路中的交叉耦合晶体管对提供响应于第一差分信号放大第一差分信号的负电阻。 通过储能电路，缓冲器和积分电路的电流基本上彼此相同，并与控制振荡频率的外部施加的参考电流一致地移动。 结果，振荡器可以实现宽范围的振荡频率。 缓冲器向共模环路增加180度的相移，从而提供防止锁定的负共模反馈。 储能电路，缓冲器和积分电路使用差分晶体管对，减少由于外部共模噪声源引起的相位抖动。

公开(公告)号：US08918752B2

公开(公告)日：2014-12-23

申请号：US13326301

申请日：2011-12-14

申请人： Alex Chow ,  Robert J. Drost ,  Ronald Ho ,  Robert D. Hopkins ,  Ivan E. Sutherland

发明人： Alex Chow ,  Robert J. Drost ,  Ronald Ho ,  Robert D. Hopkins ,  Ivan E. Sutherland

IPC分类号： G06F17/50

CPC分类号： H01L23/585 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/72 ,  H01L25/0657 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/292 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/83851 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.

摘要翻译： 描述半导体管芯。 该半导体管芯包括驱动器和电耦合到驱动器并且靠近半导体管芯的表面的空间对准换能器。 驱动器在空间对准转换器中在至少一个方向上建立空间变化的电荷分布，从而有助于确定半导体管芯和另一个半导体管芯之间的多于一个方向上的空间对准。 特别地，靠近另一个半导体管芯的表面的空间对准传感器可以检测与空间变化的电荷分布相关联的电场（或相关的静电电位）。 该检测的电场可以允许确定半导体管芯的表面之间的垂直间隔和/或半导体管芯的角度对准。

公开(公告)号：US08735184B2

公开(公告)日：2014-05-27

申请号：US13341175

申请日：2011-12-30

申请人： Ronald Ho ,  Robert D. Hopkins ,  William S. Coates ,  Robert J. Drost

发明人： Ronald Ho ,  Robert D. Hopkins ,  William S. Coates ,  Robert J. Drost

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.

摘要翻译： 一种器件包括具有表面的半导体管芯，靠近表面的多个接近连接器，以及耦合到多个接近连接器中的至少一个的电路。 半导体管芯被配置为通过使用多个接近连接器中的一个或多个的电容耦合来传送电压模式信号。 电路还包括具有电容求和结的滤波器以均衡信号。

公开(公告)号：US08644759B2

公开(公告)日：2014-02-04

申请号：US12349011

申请日：2009-01-06

申请人： Justin M. Schauer ,  Robert David Hopkins ,  Robert J. Drost

发明人： Justin M. Schauer ,  Robert David Hopkins ,  Robert J. Drost

IPC分类号： H04B5/00

CPC分类号： H03F3/45179 ,  H03F1/0261 ,  H03F3/45475 ,  H03F3/45973 ,  H03F2200/534 ,  H03F2200/537 ,  H03F2200/54 ,  H03F2200/541 ,  H03F2203/45101 ,  H03F2203/45212 ,  H03F2203/45518 ,  H03F2203/45524 ,  H03F2203/45528 ,  H04B5/0031

摘要： Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.

摘要翻译： 在与输入到放大器的数据信号直流隔离的高性能放大器的输入上开发的浮动电压上的偏移电压通过在输入节点和预定电位之间连接高电阻元件而被消除，在邻近通信系统中特别有用，其中两个 芯片通过在两个芯片中共同形成的电容或电感耦合电路连接。 电阻元件可以是连接在节点和期望偏置电压之间的截止MOS晶体管，或者其栅极和漏极连接到电位的MOS晶体管。 可以将多个偏置电压分配给所有接收器，并由多路复用器本地选择以应用于接收器的一个或两个输入节点。 当电阻元件与数据速率相比具有长时间常数或电阻元件是非线性时，接收器输出也可以用作预定电位。

公开(公告)号：US08472206B2

公开(公告)日：2013-06-25

申请号：US13235152

申请日：2011-09-16

申请人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

发明人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： G06F1/189

摘要： One embodiment of the present invention provides a method that reduces power consumption by using capacitive coupling to perform a majority detection operation. The method involves driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. In addition, method involves feeding a signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The method further involves using the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by a computer system.

摘要翻译： 本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的方法。 该方法涉及将多个信号驱动到多个从动导线上。 然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。 此外，方法包括将多个检测线上的信号和偏置电压馈送到差分接收器。 如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。 该方法还包括使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。 优化信号传输减少了计算机系统消耗的功耗。