利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

115 条记录 (耗时 0.035 秒)

    Thin film etching method and semiconductor device fabrication using same
    72.
    发明授权
    Thin film etching method and semiconductor device fabrication using same 有权
    薄膜蚀刻方法和使用其的半导体器件制造

    公开(公告)号：US07879732B2

    公开(公告)日：2011-02-01

    申请号：US11959034

    申请日：2007-12-18

    申请人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

    发明人： Xiang Hu ,  Hai Cong ,  Pradeep Yelehanka ,  Mei Sheng Zhou

    IPC分类号： H01L21/302 ,  G01R31/00 ,  B44C1/22

    CPC分类号： H01J37/32963 ,  H01J37/32935

    摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.

    摘要翻译： 一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻 移除端点检测层。 端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。 当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

    High shrinkage stress silicon nitride (SiN) layer for NFET improvement
    73.
    发明申请
    High shrinkage stress silicon nitride (SiN) layer for NFET improvement 审中-公开
    用于NFET改进的高收缩应力氮化硅（SiN）层

    公开(公告)号：US20090289284A1

    公开(公告)日：2009-11-26

    申请号：US12154605

    申请日：2008-05-23

    申请人： Luona Goh ,  Jingze Tian ,  Wei Lu ,  Mei Sheng Zhou

    发明人： Luona Goh ,  Jingze Tian ,  Wei Lu ,  Mei Sheng Zhou

    IPC分类号： H01L29/78 ,  H01L21/3105

    CPC分类号： H01L21/3125 ,  H01L21/0217 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02348 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region.

    摘要翻译： 在应力管理技术（SMT）中形成用作接触蚀刻停止层（CESL）或封盖层的高收缩应力氮化硅层的方法（和半导体器件）提供了对nFET器件的沟道增加的拉伸应力， 增强载体流动性。 将旋涂聚硅氮烷基介电材料施加到半导体衬底上并烘烤以形成膜层。 固化膜层以从膜中除去氢，当其重结晶成氮化硅时，其导致膜的收缩。 所得的氮化硅应力层向晶体管沟道区域引入增加的拉伸应力水平。

    Method of using silicon rich carbide as a barrier material for fluorinated materials
    77.
    发明授权
    Method of using silicon rich carbide as a barrier material for fluorinated materials 失效
    使用富碳化碳作为氟化材料的阻挡材料的方法

    公开(公告)号：US06730591B2

    公开(公告)日：2004-05-04

    申请号：US10186532

    申请日：2002-07-01

    申请人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

    发明人： Licheng Han ,  Xu Yi ,  Simon Chooi ,  Mei Sheng Zhou ,  Joseph Zhifeng Xie

    IPC分类号： H01L214763

    CPC分类号： H01L21/76834 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

    摘要： A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

    摘要翻译： 一种在半导体器件中形成互连结构的方法，包括以下步骤。 提供半导体结构。 在第一实施例中，在半导体结构上形成至少一条金属线。 在金属线和半导体结构之上形成富含碳的碳化物阻挡层。 最后，在富含硅的碳化物层上形成可被氟化的介电层。 在第二实施例中，在半导体结构上形成至少一个可被氟化的氟化介电层。 图案化电介质层以在其中形成开口。 在开口内形成富含碳的碳化物阻挡层。 在结构上沉积金属化层，填充富含硅的碳化物阻挡层衬里的开口。 最后，金属化层可以被平坦化以在富含硅的碳化物阻挡层衬里的开口内形成平坦化的金属结构。

    Method to improve etching of organic-based, low dielectric constant materials
    78.
    发明授权
    Method to improve etching of organic-based, low dielectric constant materials 失效
    改善有机系低介电常数材料蚀刻的方法

    公开(公告)号：US06524963B1

    公开(公告)日：2003-02-25

    申请号：US09421510

    申请日：1999-10-20

    申请人： Mei Sheng Zhou ,  Simon Chooi ,  Jian Xun Li

    发明人： Mei Sheng Zhou ,  Simon Chooi ,  Jian Xun Li

    IPC分类号： H01L21302

    CPC分类号： H01L21/31116 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/76802

    摘要： A method etching an organic-based, low dielectric constant material in the manufacture of an integrated circuit device has been achieved. Organic materials without silicon and organic materials without fluorine can be etched by using, for example, hydrazine or ammonia gas. Organic materials with silicon can also be etched with the addition of a fluorine-containing or chlorine-containing gas. A semiconductor substrate is provided. A low dielectric constant organic-based material is deposited overlying the semiconductor substrate. The low dielectric constant organic-based material is etched to form desirable features using a plasma containing a gas comprising a nitrogen and hydrogen containing molecule, and the integrated circuit device is completed.

    摘要翻译： 已经实现了在制造集成电路器件中蚀刻有机基低介电常数材料的方法。 不含硅的有机材料和无氟的有机材料可以通过使用例如肼或氨气进行蚀刻。 也可以通过添加含氟或含氯气体来蚀刻具有硅的有机材料。 提供半导体衬底。 沉积在半导体衬底上的低介电常数有机基材料。 使用包含含有氮和氢的分子的气体的等离子体来蚀刻低介电常数有机基材料以形成期望的特征，并且完成集成电路器件。

    Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene
    79.
    发明授权
    Composite silicon-metal nitride barrier to prevent formation of metal fluorides in copper damascene 有权
    复合硅 - 金属氮化物屏障，以防铜铜镶嵌中金属氟化物的形成

    公开(公告)号：US06465888B2

    公开(公告)日：2002-10-15

    申请号：US10043604

    申请日：2002-01-14

    申请人： Simon Chooi ,  Subhash Gupta ,  Mei Sheng Zhou ,  Sang Ki Hong

    发明人： Simon Chooi ,  Subhash Gupta ,  Mei Sheng Zhou ,  Sang Ki Hong

    IPC分类号： H01L2352

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76855

    摘要： A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure—single, dual, or multi-structure—is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer. In the third embodiment, the ternary metal silicon nitride spacer is formed by etching after having first formed the amorphous silicon layer and the nitride layer, in that order, and then etching the passivation/barrier layer at the bottom of the damascene structure into the underlying copper layer. In all three embodiments, metal nitride reacts with amorphous silicon to form a ternary metal silicon nitride having an excellent property of adhering to copper while at the same time for forming an excellent barrier to diffusion of copper.

    摘要翻译： 公开了一种形成非晶硅间隔物的方法，随后在铜镶嵌结构 - 单，双或多结构中在间隔物上形成金属氮化物，以防止铜中氟化物的形成。 在第一实施例中，通过在形成在内部的非晶硅间隔物上形成金属氮化物层之后，通过从双镶嵌结构形成开口到下面的铜层来形成铜镶嵌层和下面的铜金属层之间的互连 双镶嵌结构的墙壁。 在第二实施例中，通过在形成非晶硅间隔物之后并且在形成金属氮化物层之前通过蚀刻到下面的铜层中，由双镶嵌结构制造双镶嵌结构和下面的铜线之间的互连。 在第三实施例中，三元金属氮化硅间隔物依次先形成非晶硅层和氮化物层后，通过蚀刻形成，然后在镶嵌结构底部蚀刻钝化/阻挡层，形成底层 铜层。 在所有三个实施例中，金属氮化物与非晶硅反应形成具有优异的粘附铜特性的三元金属氮化硅，同时形成对铜的扩散的优异屏障。

    Low dielectric constant materials for copper damascene
    80.
    发明授权
    Low dielectric constant materials for copper damascene 有权
    用于铜镶嵌的低介电常数材料

    公开(公告)号：US06436824B1

    公开(公告)日：2002-08-20

    申请号：US09346526

    申请日：1999-07-02

    申请人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

    发明人： Simon Chooi ,  Mei Sheng Zhou ,  Yi Xu

    IPC分类号： H01L2144

    CPC分类号： H01L21/02211 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/3125 ,  H01L21/314 ,  H01L21/76807

    摘要： Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

    摘要翻译： 提供了用于双镶嵌工艺中的电介质的新型低介电常数材料。 通过在等离子体增强化学沉积室中使含氮前体和取代的有机硅烷反应形成低介电常数材料介电层。 此外，提供了用于双镶嵌工艺中的钝化或蚀刻停止层的新型低介电常数材料。 通过在等离子体增强化学沉积室中使取代的氨前体和取代的有机硅烷反应形成具有低介电约束的碳掺杂的氮化硅钝化或蚀刻停止层。 或者，通过在等离子体增强化学沉积室中使取代的有机硅烷反应形成具有低介电常数的碳化硅钝化或蚀刻停止层。 此外，描述了形成用于双镶嵌工艺中的钝化，电介质和蚀刻停止层的集成工艺。