公开(公告)号：US4737226A

公开(公告)日：1988-04-12

申请号：US824968

申请日：1986-01-31

申请人： Hirofumi Inoue

发明人： Hirofumi Inoue

IPC分类号： B68G7/05 ,  B29C43/18 ,  B29C63/00 ,  B29C63/02 ,  B29C63/22 ,  B29C65/00 ,  B29C65/50 ,  B68G7/00 ,  B68G7/052 ,  B32B31/20 ,  B29C33/40

CPC分类号： B68G7/052 ,  B29C43/18 ,  B29C63/00 ,  B29C63/025 ,  B29C63/22 ,  B29C65/18 ,  B29C65/4815 ,  B29C65/5028 ,  B29C65/5057 ,  B29C66/5326 ,  B29C66/727 ,  B29C66/729 ,  B29C66/7485 ,  B29C66/8322 ,  B29C65/7847 ,  B29C66/71 ,  B29K2023/06 ,  B29K2075/00 ,  B29L2031/3005 ,  B29L2031/3041 ,  B29L2031/751 ,  B29L2031/771

摘要： A method of manufacturing an automotive seat is disclosed which comprises the step of placing a trim cover assembly over a cushion member of foam material. In the method, a thermally weldable adhesive cloth is interposed between the trim cover assembly and the cushion member and is then welded by means of heating/pressure operation so that the trim cover assembly can be adhesively attached to the surface of the cushion member. Thus, the method provides such a seat that is improved in finishing as well as durability.

摘要翻译： 公开了一种制造汽车座椅的方法，其包括将装饰罩组件放置在泡沫材料的缓冲构件上的步骤。 在该方法中，将可热焊接的粘合剂布置在装饰罩组件和缓冲构件之间，然后通过加热/压力操作进行焊接，使得装饰罩组件可以粘附到缓冲构件的表面。 因此，该方法提供了在整理以及耐久性方面得到改进的座位。

公开(公告)号：US08391082B2

公开(公告)日：2013-03-05

申请号：US13099540

申请日：2011-05-03

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2216/24

摘要： A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

摘要翻译： 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元 两行之间的第一和第二行的交点，每个存储单元包含以电阻作为数据以非易失性方式存储的电可擦除可编程可变电阻元件; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。 多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。

公开(公告)号：US08391048B2

公开(公告)日：2013-03-05

申请号：US12846198

申请日：2010-07-29

申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

IPC分类号： G11C11/00

CPC分类号： G11C13/0061 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

公开(公告)号：US08318602B2

公开(公告)日：2012-11-27

申请号：US13085622

申请日：2011-04-13

申请人： Masaru Kito ,  Hirofumi Inoue

发明人： Masaru Kito ,  Hirofumi Inoue

IPC分类号： H01L21/768

CPC分类号： H01L27/105 ,  G11C16/10 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储装置，包括：基板; 垂直于衬底设置的柱状半导体; 设置在所述柱状半导体周围的电荷存储层叠膜; 与所述电荷存储叠层膜接触并具有第一端部的第一导体层，所述第一端部具有第一端面; 与电荷存储叠层膜接触的第二导体层，其与第一导体层分离并且具有具有第二端面的第二端部; 设置在所述第一端面上的第一接触插塞; 以及设置在所述第二端面上的第二接触插塞。

公开(公告)号：US08285448B2

公开(公告)日：2012-10-09

申请号：US12440183

申请日：2007-08-28

申请人： Hirofumi Inoue ,  Hideshi Watanabe ,  Takuhiro Kondo

发明人： Hirofumi Inoue ,  Hideshi Watanabe ,  Takuhiro Kondo

IPC分类号： B60G17/018 ,  B60G23/00 ,  B60G17/0185 ,  B60G17/04 ,  B60G17/015 ,  B60G17/052 ,  B60G17/02 ,  B60G17/00 ,  B62C3/00 ,  B62K25/00 ,  G06F7/00 ,  G06F17/00 ,  G06F19/00 ,  B60P1/00 ,  B60S9/00

CPC分类号： B60G17/0157 ,  B60G15/08 ,  B60G17/0155 ,  B60G17/018 ,  B60G17/0521 ,  B60G17/06 ,  B60G2202/152 ,  B60G2202/314 ,  B60G2202/42 ,  B60G2204/126 ,  B60G2204/419 ,  B60G2204/4232 ,  B60G2204/62 ,  B60G2400/0511 ,  B60G2400/0516 ,  B60G2400/102 ,  B60G2400/104 ,  B60G2400/106 ,  B60G2400/204 ,  B60G2400/252 ,  B60G2400/33 ,  B60G2400/382 ,  B60G2400/39 ,  B60G2400/41 ,  B60G2400/716 ,  B60G2400/73 ,  B60G2500/201 ,  B60G2500/2021 ,  B60G2500/203 ,  B60G2500/30 ,  B60G2600/02 ,  B60G2600/07 ,  B60G2600/08 ,  B60G2600/182 ,  B60G2800/012 ,  B60G2800/014 ,  B60G2800/162 ,  B60G2800/80 ,  B60G2800/9122 ,  B60G2800/914 ,  B60G2800/916 ,  F16F2232/04 ,  F16F2232/06

摘要： It is an object of the invention to provide a suspension system configured to execute a control for avoiding a state in which an operation of an electric motor which is a power source of an electromagnetic actuator is kept halted at a certain operational position while the motor is generating a motor force. Where a target rotational position of the motor becomes equal to a specific operational position (e.g., a rotational position at which an electrifying current amount of one phase reaches a peak value), a control for shifting the target rotational position by δθ is executed. Where the rotational position of the motor is kept located at the certain position for a time period longer than a prescribed time, a control for changing the rotational position of the motor is executed. According to the present suspension system, it is possible to suppress imbalance in heat generation in the motor and to thereby reduce a load to be applied to the motor. Accordingly, a suspension system with high utility is realized.

摘要翻译： 本发明的目的是提供一种悬架系统，该悬架系统被配置为执行控制，以避免将电动机作为电动机的电源的电动机的动作在马达为 产生马达力。 在电动机的目标旋转位置变得等于特定操作位置（例如，一相通电电流量达到峰值的旋转位置）的情况下，将目标旋转位置移位δ控制的控制; 被执行。 在电动机的旋转位置保持在特定位置上比规定时间长的时间的情况下，执行用于改变电动机的旋转位置的控制。 根据本悬架系统，可以抑制电动机的发热不平衡，从而减小对电动机施加的负荷。 因此，实现了高效率的悬架系统。

公开(公告)号：US08183602B2

公开(公告)日：2012-05-22

申请号：US12275682

申请日：2008-11-21

申请人： Hideyuki Tabata ,  Eiji Ito ,  Hirofumi Inoue

发明人： Hideyuki Tabata ,  Eiji Ito ,  Hirofumi Inoue

IPC分类号： H01L23/52

CPC分类号： H01L27/2481 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines indifferent cell array layers.

摘要翻译： 非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。 通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔连接到第一或第二线不同的单元阵列层。

公开(公告)号：US08103408B2

公开(公告)日：2012-01-24

申请号：US12091385

申请日：2006-10-25

申请人： Hirofumi Inoue ,  Takuhiro Kondo ,  Yoshihiro Suda

发明人： Hirofumi Inoue ,  Takuhiro Kondo ,  Yoshihiro Suda

IPC分类号： B60G17/015

CPC分类号： F16F15/03 ,  B60G17/06 ,  B60G2202/42 ,  B60G2400/102 ,  B60G2400/104 ,  B60G2400/106 ,  B60G2400/204 ,  B60G2400/252 ,  B60G2400/41 ,  B60G2500/10 ,  B60G2800/012 ,  B60G2800/014

摘要： In a system including four electromagnetic absorbers for respective four vehicle wheels, motor coils of two respective electromagnetic absorbers disposed corresponding to two diagonally located wheels are connected forming a closed loop including the coils. A generated damping force magnitude can be made different between an instance directions of respective movements of the diagonally located two wheels with respect to the vehicle body are the same, and an instance the directions are opposite each other. Each electromagnetic absorber includes a resistor cooperating with the corresponding coil forming a closed loop, and selectively establishes: a connected state in which one of the four coils and any of the other three coils are connected to form a closed loop; and a non-connected state in which the one of the four coils is not connected to any other coil. An appropriate vibration suppressing action is exhibited with respect to a coupled motion.

摘要翻译： 在包括用于相应的四个车轮的四个电磁吸收器的系统中，连接两个对应于两个对角定位的车轮设置的两个相应的电磁吸收器的电机线圈，形成包括线圈的闭合回路。 在相对于车身的对角位置的两个车轮的各个运动的实例方向相同的情况下，可以使所产生的阻尼力大小不同，并且方向彼此相反。 每个电磁吸收器包括与形成闭环的相应线圈配合的电阻器，并且选择性地建立：连接状态，其中四个线圈中的一个线圈和任何其他三个线圈中的一个被连接以形成闭环; 以及四个线圈中的一个未连接到任何其它线圈的非连接状态。 相对于耦合运动而言，显示适当的振动抑制动作。

公开(公告)号：US20120012807A1

公开(公告)日：2012-01-19

申请号：US13182095

申请日：2011-07-13

申请人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

发明人： Takeshi YAMAGUCHI ,  Hirofumi Inoue ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Takashi Shigeoka ,  Katsuyuki Sekine ,  Shinya Aoki

IPC分类号： H01L45/00

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233

摘要： A semiconductor memory device in an embodiment comprises memory cells, each of the memory cells disposed between a first line and a second line and having a variable resistance element and a switching element connected in series. The variable resistance element includes a variable resistance layer configured to change in resistance value thereof between a low-resistance state and a high-resistance state. The variable resistance layer is configured by a transition metal oxide. A ratio of transition metal and oxygen configuring the transition metal oxide varies between 1:1 and 1:2 along a first direction directed from the first line to the second line.

摘要翻译： 实施例中的半导体存储器件包括存储单元，每个存储单元设置在第一线和第二线之间，并且具有串联连接的可变电阻元件和开关元件。 可变电阻元件包括可变电阻层，其被配置为在低电阻状态和高电阻状态之间改变其电阻值。 可变电阻层由过渡金属氧化物构成。 构成过渡金属氧化物的过渡金属和氧的比例沿着从第一线指向第二线的第一方向在1:1和1:2之间变化。

公开(公告)号：US20110189853A1

公开(公告)日：2011-08-04

申请号：US13085622

申请日：2011-04-13

申请人： Masaru Kito ,  Hirofumi Inoue

发明人： Masaru Kito ,  Hirofumi Inoue

IPC分类号： H01L21/768

CPC分类号： H01L27/105 ,  G11C16/10 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储装置，包括：基板; 垂直于衬底设置的柱状半导体; 设置在所述柱状半导体周围的电荷存储层叠膜; 与所述电荷存储叠层膜接触并具有第一端部的第一导体层，所述第一端部具有第一端面; 与电荷存储叠层膜接触的第二导体层，其与第一导体层分离并且具有具有第二端面的第二端部; 设置在所述第一端面上的第一接触插塞; 以及设置在所述第二端面上的第二接触插塞。

公开(公告)号：US07957203B2

公开(公告)日：2011-06-07

申请号：US12511443

申请日：2009-07-29

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2216/24

摘要： A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

摘要翻译： 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元 两行之间的第一和第二行的交点，每个存储单元包含电可擦除可编程可变电阻元件，其电阻被非挥发性地存储为数据; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。 多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。