公开(公告)号：US10658381B1

公开(公告)日：2020-05-19

申请号：US16367455

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Fumiaki Toyama ,  Masaaki Higashitani ,  Tong Zhang ,  Chun Ge ,  Xin Yuan Li ,  Johann Alsmeier

IPC: H01L27/11565 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/11573

Abstract: Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.

公开(公告)号：US20200143889A1

公开(公告)日：2020-05-07

申请号：US16233780

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

公开(公告)号：US20200013794A1

公开(公告)日：2020-01-09

申请号：US16141163

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: H01L27/11578 ,  G11C16/28 ,  G11C11/24 ,  G11C16/24 ,  G11C16/30 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US10510738B2

公开(公告)日：2019-12-17

申请号：US16243469

申请日：2019-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Masaaki Higashitani ,  Fumiaki Toyama ,  Akio Nishida

IPC: H01L23/52 ,  H01L27/11582 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US10319680B1

公开(公告)日：2019-06-11

申请号：US15909036

申请日：2018-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun Sel ,  Masaaki Higashitani ,  Mohan Dunga ,  Fumiaki Toyama ,  Peter Rabkin

IPC: H01L23/52 ,  H01L23/532 ,  H01L27/11556 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582

Abstract: A structure includes a metal interconnect structure embedded in a lower interconnect level dielectric layer overlying a substrate, at least one material layer overlying the metal interconnect structure, a first contact level dielectric layer overlying the at least one material layer; a metal contact via structure vertically extending through the first contact level dielectric layer and the at least one material layer and contacting a top surface of the metal interconnect structure, and an encapsulated tubular cavity laterally surrounding at least a lower portion of the metal contact via structure, and vertically extending through the at least one material layer.

公开(公告)号：US09711229B1

公开(公告)日：2017-07-18

申请号：US15246510

申请日：2016-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  H01L27/115 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/145 ,  H01L45/146

Abstract: Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more shared word lines. In cases where a first vertical NAND string of the first set and a second vertical NAND string of the second set are both connected to selected bit lines and the same shared word line, selectivity of memory cells may be provided by applying different voltages to the first drain-side select line and the second drain-side select line.

公开(公告)号：US20170062068A1

公开(公告)日：2017-03-02

申请号：US15352390

申请日：2016-11-15

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the

Abstract translation: 描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。 存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。 在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。 在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时 存储器阵列和组内的未选择字线的位置

公开(公告)号：US12219756B2

公开(公告)日：2025-02-04

申请号：US17664550

申请日：2022-05-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B41/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance of the semiconductor channel. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

公开(公告)号：US12009269B2

公开(公告)日：2024-06-11

申请号：US17725695

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Masaaki Higashitani ,  Yusuke Ikawa ,  Seyyed Ehsan Esfahani Rashidi ,  Kei Samura ,  Tsuyoshi Sendoda ,  Yanli Zhang

IPC: H01L21/66 ,  H01L27/11578 ,  H10B43/20 ,  H10B43/10

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/26 ,  H10B43/20 ,  H10B43/10

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US12004348B2

公开(公告)日：2024-06-04

申请号：US17347810

申请日：2021-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  Fumiaki Toyama ,  Masaaki Higashitani

IPC: H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A bonded assembly includes a memory die that is bonded to a logic die. The memory die includes a three-dimensional memory array located on a memory-side substrate, memory-side dielectric material layers located on the three-dimensional memory array and embedding memory-side metal interconnect structures and memory-side bonding pads, a backside peripheral circuit located on a backside surface of the memory-side substrate, and backside dielectric material layers located on a backside of the memory-side substrate and embedding backside metal interconnect structures. The logic die includes a logic-side peripheral circuit located on a logic-side substrate, and logic-side dielectric material layers located between the logic-side substrate and the memory die and embedding logic-side metal interconnect structures and logic-side bonding pads that are bonded to a respective one of the memory-side bonding pads.