公开(公告)号：US20180076195A1

公开(公告)日：2018-03-15

申请号：US15814569

申请日：2017-11-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Shinya SASAGAWA

IPC: H01L27/06 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L27/0688 ,  H01L21/76805 ,  H01L27/092 ,  H01L27/1156 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To fabricate an integrated circuit, a first insulating film is formed over a p-channel transistor; a transistor including an oxide semiconductor is formed over the first insulating film; a second insulating film is formed over the transistor; an opening, that is, a contact hole part of a sidewall of which is formed of the oxide semiconductor of the transistor, is formed in the first insulating film and the second insulating film; and an electrode connecting the p-channel transistor and the transistor including an oxide semiconductor to each other is formed.

公开(公告)号：US20170358685A1

公开(公告)日：2017-12-14

申请号：US15669234

申请日：2017-08-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786 ,  H01L27/1156 ,  H01L29/66

CPC classification number: H01L29/78606 ,  H01L27/1156 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

公开(公告)号：US20170288064A1

公开(公告)日：2017-10-05

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/46 ,  H01L29/66 ,  H01L21/425

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US20170200828A1

公开(公告)日：2017-07-13

申请号：US15467288

申请日：2017-03-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji EGI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L21/44 ,  H01L21/4757 ,  H01L29/66 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/04 ,  H01L21/02 ,  H01L21/465

CPC classification number: H01L29/7869 ,  H01L21/0206 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/465 ,  H01L21/4757 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/14616 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78693

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

公开(公告)号：US20170062619A1

公开(公告)日：2017-03-02

申请号：US15235242

申请日：2016-08-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Takashi HAMADA ,  Akihisa SHIMOMURA ,  Satoru OKAMOTO ,  Katsuaki TOCHIBAYASHI

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/4763 ,  H01L21/465 ,  H01L29/423 ,  H01L21/4757

CPC classification number: H01L29/7869 ,  H01L21/465 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42372 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor.

Abstract translation: 提供一分钟晶体管。 提供具有低寄生电容的晶体管。 提供具有高频特性的晶体管。 提供具有高导通状态电流的晶体管。 提供包括晶体管的半导体器件。 提供了具有高集成度的半导体器件。 一种包括氧化物半导体的半导体器件; 第二绝缘体; 第二导体 第三导体; 第四导体 第五个指挥 嵌入在形成于第二绝缘体的开口部的第一导体和第一绝缘体，第二导​​体，第三导体，第四导体和第五导体; 第二导体的侧表面和底表面与第四导体接触的区域; 以及第三导体的侧表面和底表面与第五导体接触的区域。

公开(公告)号：US20170012139A1

公开(公告)日：2017-01-12

申请号：US15193564

申请日：2016-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/321 ,  H01L21/306

CPC classification number: H01L29/78693 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.

Abstract translation: 提供一分钟晶体管。 提供具有小寄生电容的晶体管。 提供了具有高频特性的晶体管。 提供包括晶体管的半导体器件。 半导体器件包括氧化物半导体，第一导体和嵌入第一绝缘体中的第二绝缘体，第二导​​体和第三导体。 第二导体和第三导体彼此面对的边缘具有30度以上且90度以下的锥角。

公开(公告)号：US20160351589A1

公开(公告)日：2016-12-01

申请号：US15234155

申请日：2016-08-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hidekazu MIYAIRI ,  Shunpei YAMAZAKI ,  Motomu KURATA

IPC: H01L27/12 ,  H01L27/092 ,  H01L27/105 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L21/8221 ,  H01L27/0922 ,  H01L27/1052 ,  H01L27/1128 ,  H01L27/1207 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1259 ,  H01L27/127 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.

公开(公告)号：US20160240690A1

公开(公告)日：2016-08-18

申请号：US15137621

申请日：2016-04-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/26 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/7869

Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for a metal film of a source electrode layer and a drain electrode layer, whereby diffusion of oxygen to the metal film is suppressed.

Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层和漏电极层的金属膜，从而抑制氧向金属膜的扩散。

公开(公告)号：US20160218219A1

公开(公告)日：2016-07-28

申请号：US14995562

申请日：2016-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Satoru OKAMOTO ,  Shinya SASAGAWA

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/475 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

Abstract translation: 半导体器件包括在第一绝缘层上的第一氧化物绝缘层，在第一氧化物绝缘层上的氧化物半导体层，氧化物半导体层上的源电极层和漏电极层，在源电极层上的第二绝缘层 漏极电极层，氧化物半导体层上的第二氧化物绝缘层，第二氧化物绝缘层上的栅极绝缘层，栅极绝缘层上的栅极电极层和第二绝缘层上的第三绝缘层， 第二氧化物绝缘层，栅极绝缘层和栅极电极层。 第二绝缘层的侧表面部分与第二氧化物绝缘层接触。 栅极电极层包括第一区域和第二区域。 第一区域的宽度大于第二区域的宽度。

公开(公告)号：US20160087105A1

公开(公告)日：2016-03-24

申请号：US14853542

申请日：2015-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Katsuaki TOCHIBAYASHI ,  Yuta ENDO ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/7869 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/78648

Abstract: A method for manufacturing a semiconductor device, including the steps of forming a semiconductor over a substrate; forming a first conductor over the semiconductor; forming a first insulator over the first conductor; forming a resist over the first insulator; performing light exposure and development on the resist to make a second region and a third region remain and expose part of the first insulator; applying a bias in a direction perpendicular to a top surface of the substrate and generating plasma using a gas containing carbon and halogen; and depositing and etching an organic substance with the plasma. The etching rate of the organic substance is higher than the deposition rate of the organic substance in an exposed part of the first insulator, and the deposition rate of the organic substance is higher than the etching rate of the organic substance in a side surface of the second region.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成半导体的步骤; 在半导体上形成第一导体; 在所述第一导体上形成第一绝缘体; 在第一绝缘体上形成抗蚀剂; 在抗蚀剂上进行曝光和显影以使第二区域和第三区域保持并暴露第一绝缘体的部分; 在垂直于衬底的顶表面的方向施加偏压并使用含有碳和卤素的气体产生等离子体; 并用等离子体沉积和蚀刻有机物质。 有机物的蚀刻速度高于第一绝缘体的露出部分中的有机物质的沉积速度，并且有机物质的沉积速度高于有机物的侧表面中的有机物质的蚀刻速率 第二区。