公开(公告)号：US20220013364A1

公开(公告)日：2022-01-13

申请号：US16923658

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

公开(公告)号：US20210376105A1

公开(公告)日：2021-12-02

申请号：US17145925

申请日：2021-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

公开(公告)号：US20210335657A1

公开(公告)日：2021-10-28

申请号：US17025528

申请日：2020-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Ting-Gang Chen ,  Sung-En Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui ,  Tai-Chun Huang ,  Chieh-Ping Wang

IPC: H01L21/762 ,  H01L21/311

Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.

公开(公告)号：US10312158B2

公开(公告)日：2019-06-04

申请号：US15670401

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Li ,  Chien-Hao Chen ,  Yung-Cheng Lu ,  Jr-Jung Lin ,  Chun-Hung Lee ,  Chao-Cheng Chen

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/108 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.

公开(公告)号：US09748109B2

公开(公告)日：2017-08-29

申请号：US15047793

申请日：2016-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US12255205B2

公开(公告)日：2025-03-18

申请号：US17826845

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping Wang ,  Tai-Chun Huang ,  Yung-Cheng Lu ,  Ting-Gang Chen ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H10B99/00

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

公开(公告)号：US12206013B2

公开(公告)日：2025-01-21

申请号：US18346020

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui ,  Hung Cheng Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

公开(公告)号：US12176349B2

公开(公告)日：2024-12-24

申请号：US18335637

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US20240387705A1

公开(公告)日：2024-11-21

申请号：US18787005

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yung-Cheng Lu ,  Che-Hao Chang ,  Chi On Chui ,  Hung Cheng Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

公开(公告)号：US20240347623A1

公开(公告)日：2024-10-17

申请号：US18753240

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.