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    MULTI-PRESSURE MEMS PACKAGE
    72.
    发明申请
    MULTI-PRESSURE MEMS PACKAGE 审中-公开

    公开(公告)号：US20170283250A1

    公开(公告)日：2017-10-05

    申请号：US15626764

    申请日：2017-06-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Kuei-Sung Chang ,  Jung-Huei Peng

    IPC: B81B7/04 ,  B81C1/00

    CPC classification number: B81B3/0051 ,  B81B7/02 ,  B81C2203/0118

    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package having two MEMS devices with different pressures, and an associated method of formation. In some embodiments, the (MEMS) package includes a device substrate and a cap substrate bonded together. The device substrate includes a first trench and a second trench. A first MEMS device is disposed over the first trench and a second MEMS device is disposed over the second trench. A first stopper is raised from a first trench bottom surface of the first trench but below a top surface of the device substrate and a second stopper is raised from a second trench bottom surface of the second trench but below the top surface of the device substrate. A first depth of the first trench is greater than a second depth of the second trench.

    Isolation structure for MEMS 3D IC integration
    74.
    发明授权
    Isolation structure for MEMS 3D IC integration 有权
    MEMS 3D IC集成隔离结构

    公开(公告)号：US09446945B2

    公开(公告)日：2016-09-20

    申请号：US14639530

    申请日：2015-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Heng Tsai ,  Yi-Hsien Chang ,  Chun-Ren Cheng ,  Chun-Wen Cheng ,  Tzu-Heng Wu ,  Wei-Cheng Shen

    IPC: H01L31/0203 ,  B81B7/00 ,  B81C1/00

    CPC classification number: B81C1/00238 ,  B81B7/0048

    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.

    Abstract translation: 三维（3D）集成电路（IC）包括第一IC和第二IC。 第一IC包括MEMS器件和第一接合结构。 第二IC包括第二接合结构。 第一和第二接合结构被结合在一起以将第一IC耦合到第二IC。 在距离第一IC最近的第二IC的表面上设置保形阻挡层。 蚀刻隔离结构被布置在第二IC的表面下方并且包围一个牺牲区域，该牺牲区域被布置在第二接合结构的任一侧上并且被布置在第二IC中。

    MONOLITHIC COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) - INTEGRATED SILICON MICROPHONE
    75.
    发明申请
    MONOLITHIC COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) - INTEGRATED SILICON MICROPHONE 有权
    单相补充金属氧化物半导体（CMOS） - 集成硅麦克风

    公开(公告)号：US20160241979A1

    公开(公告)日：2016-08-18

    申请号：US14620368

    申请日：2015-02-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Yi Cho ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng ,  Yao-Te Huang

    IPC: H04R31/00 ,  H04R19/04

    CPC classification number: H04R1/04 ,  H04R19/005 ,  H04R19/04

    Abstract: Some embodiments relate to a manufacturing process that combines a MEMS capacitor of a microelectromechanical systems (MEMS) microphone and an integrated circuit (IC) onto a single substrate. A dielectric is formed over a device substrate. A conductive diaphragm and a conductive backplate are formed within the dielectric, with a sacrificial portion of the dielectric between them. A first recess is formed, which extends through the dielectric to an upper surface of the conductive diaphragm. A second recess is formed, which extends through the substrate and dielectric to a lower surface of the conductive backplate. The sacrificial layer is removed to create an air gap between the conductive diaphragm and the conductive backplate. The air gap joins the first and second recesses to form a cavity that extends continuously through the dielectric and the substrate. The present disclosure is also directed to the semiconductor structure of the MEMS microphone resulting from the manufacturing process.

    Abstract translation: 一些实施例涉及将微机电系统（MEMS）麦克风的MEMS电容器和集成电路（IC）组合到单个基板上的制造工艺。 在器件衬底上形成电介质。 导电隔膜和导电背板形成在电介质内，电介质的牺牲部分在它们之间。 形成第一凹部，其延伸穿过电介质到导电隔膜的上表面。 形成第二凹槽，其延伸穿过基板和电介质到导电背板的下表面。 去除牺牲层以在导电隔膜和导电背板之间产生气隙。 空气间隙连接第一和第二凹部以形成连续延伸通过电介质和基底的空腔。 本公开还涉及由制造过程产生的MEMS麦克风的半导体结构。

    MEMS and CMOS integration with low-temperature bonding
    76.
    发明授权
    MEMS and CMOS integration with low-temperature bonding 有权
    MEMS和CMOS集成低温接合

    公开(公告)号：US09394161B2

    公开(公告)日：2016-07-19

    申请号：US14639492

    申请日：2015-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wen Cheng ,  Chia-Hua Chu ,  Jung-Huei Peng

    IPC: H01L21/58 ,  B81C1/00 ,  B81B3/00 ,  B81B7/00

    CPC classification number: B81C1/00238 ,  B81B3/001 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2201/0132 ,  B81C2203/035 ,  B81C2203/037 ,  B81C2203/0792 ,  H01L2224/16

    Abstract: The present disclosure relates to method of forming a MEMS device that mitigates the above mentioned difficulties. In some embodiments, the present disclosure relates to a method of forming a MEMS device, which forms one or more cavities within a first side of a carrier substrate. The first side of the carrier substrate is then bonded to a dielectric layer disposed on a micro-electromechanical system (MEMS) substrate, and the MEMS substrate is subsequently patterned to define a soft mechanical structure over the one or more cavities. The dielectric layer is then selectively removed, using a dry etching process, to release the one or more soft mechanical structures. A CMOS substrate is bonded to a second side of the MEMS substrate, by way of a bonding structure disposed between the CMOS substrate and the MEMS substrate, using a low-temperature bonding process.

    Abstract translation: 本公开涉及形成减轻上述困难的MEMS器件的方法。 在一些实施例中，本公开涉及一种形成MEMS器件的方法，所述MEMS器件在载体衬底的第一侧内形成一个或多个空腔。 然后将载体衬底的第一侧接合到布置在微机电系统（MEMS）衬底上的电介质层，随后将MEMS衬底图案化以限定一个或多个空腔上的软机械结构。 然后使用干蚀刻工艺选择性地去除电介质层以释放一个或多个软机械结构。 通过使用低温接合工艺，通过设置在CMOS衬底和MEMS衬底之间的接合结构将CMOS衬底结合到MEMS衬底的第二侧。

    INTEGRATED BIOSENSOR
    77.
    发明申请
    INTEGRATED BIOSENSOR 有权
    集成生物传感器

    公开(公告)号：US20160178568A1

    公开(公告)日：2016-06-23

    申请号：US14573162

    申请日：2014-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Wen Cheng ,  Fei-Lung Lai ,  Chia-Hua Chu ,  Yi-Hsien Chang ,  Hsin-Chieh Huang

    IPC: G01N27/414 ,  H01L21/48 ,  H01L23/498

    CPC classification number: G01N27/4148 ,  G01N27/4145 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor having horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a semiconductor substrate. A back-end-of the line (BEOL) metallization stack with a plurality of metal interconnect layers electrically coupled to the sensing device is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. A sensing well is located within a top surface of the ILD layer. The sensing well has a horizontal sensing surface extending along a top surface of a first one of the plurality of metal interconnect layers and a vertical sensing surface extending along a sidewall of a second one of the plurality of metal interconnect layers overlying the first one of the plurality of metal interconnect layers. The use of both horizontal and vertical sensing surfaces enables more accurate sensing.

    Abstract translation: 本公开涉及具有集成的生物传感器的集成芯片，其具有水平和垂直的感测表面。 在一些实施例中，集成芯片具有设置在半导体衬底内的感测装置。 具有电耦合到感测装置的多个金属互连层的线路后端（BEOL）金属化堆叠被布置在覆盖半​​导体衬底的层间电介质（ILD）层内。 感测井位于ILD层的顶表面内。 感测井具有沿着多个金属互连层中的第一个的顶表面延伸的水平感测表面和垂直感测表面，该垂直感测表面沿着多个金属互连层中的第一个上的第一个金属互连层的第二个 多个金属互连层。 使用水平和垂直传感表面可以实现更准确的感测。

    METHOD FOR THE INTEGRATION OF A MICROELECTROMECHANICAL SYSTEMS (MEMS) MICROPHONE DEVICE WITH A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE
    78.
    发明申请
    METHOD FOR THE INTEGRATION OF A MICROELECTROMECHANICAL SYSTEMS (MEMS) MICROPHONE DEVICE WITH A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE 有权
    用于集成具有补充金属氧化物半导体（CMOS）器件的微电子系统（MEMS）麦克风器件的方法

    公开(公告)号：US20160119722A1

    公开(公告)日：2016-04-28

    申请号：US14524074

    申请日：2014-10-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

    IPC: H04R19/00 ,  H04R31/00 ,  H04R19/04

    CPC classification number: H04R19/005 ,  H04R19/04 ,  H04R31/006

    Abstract: A microelectromechanical systems (MEMS) package includes a MEMS device and an integrated circuit (IC) device connected by a through silicon via (TSV). A conductive MEMS structure is arranged in a dielectric layer and includes a membrane region extending across a first volume arranged in the dielectric layer. A first substrate is bonded to a second substrate through the dielectric layer, where the MEMS device includes the second substrate. The TSV extends through the second substrate to electrically couple the MEMS device to the IC device. A third substrate is bonded to the second substrate to define a second volume between the second substrate and the third substrate, where the IC device includes the first or third substrate. A method for manufacturing the MEMS package is also provided.

    Abstract translation: 微机电系统（MEMS）封装包括MEMS器件和通过硅通孔（TSV）连接的集成电路（IC）器件。 导电MEMS结构布置在电介质层中，并且包括跨过设置在电介质层中的第一体积延伸的膜区域。 第一衬底通过介电层结合到第二衬底，其中MEMS器件包括第二衬底。 TSV延伸穿过第二衬底以将MEMS器件电耦合到IC器件。 第三衬底被结合到第二衬底以在第二衬底和第三衬底之间限定第二体积，其中IC器件包括第一或第三衬底。 还提供了一种制造MEMS封装的方法。

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