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    Structures including means for lateral current carrying capability improvement in semiconductor devices
    72.
    发明授权
    Structures including means for lateral current carrying capability improvement in semiconductor devices 有权
    结构包括用于半导体器件中横向电流承载能力改进的装置

    公开(公告)号：US07904868B2

    公开(公告)日：2011-03-08

    申请号：US11873711

    申请日：2007-10-17

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    Leakage Current Mitigation in a Semiconductor Device
    73.
    发明申请
    Leakage Current Mitigation in a Semiconductor Device 有权
    半导体器件漏电流减轻

    公开(公告)号：US20100327958A1

    公开(公告)日：2010-12-30

    申请号：US12494460

    申请日：2009-06-30

    申请人： Jong-Ru Guo ,  Louis Lu-Chen Hsu ,  Rajiv Vasant Joshi ,  Ping-Chuan Wang ,  Zhijian Yang

    发明人： Jong-Ru Guo ,  Louis Lu-Chen Hsu ,  Rajiv Vasant Joshi ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H03K3/01 ,  G01R31/26

    CPC分类号： H03K17/0822

    摘要： A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.

    摘要翻译： 识别泄漏电流目标单元内的休眠模式目标半导体器件，以减轻漏电流，防止其达到灾难性的失控。 泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点，并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流，并测量所收集的漏电流之间的差异。 比较器接收并比较当前移位监视器单元和参考电压发生器的输出。 当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时，比较器将报警信号传播到泄漏电流目标单元，表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式，其包括施加到目标半导体器件的栅极的修复​​电压发生器的修复电压。

    Metal cap for interconnect structures
    74.
    发明授权
    Metal cap for interconnect structures 有权
    用于互连结构的金属盖

    公开(公告)号：US07790599B2

    公开(公告)日：2010-09-07

    申请号：US11734958

    申请日：2007-04-13

    申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

    发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76814 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849

    摘要： A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.

    摘要翻译： 描述了形成用于互连结构的改进的金属帽的结构和方法。 该方法包括在第一绝缘层的上部形成互连特征; 在所述互连特征和所述第一绝缘层上方覆盖介电覆盖层; 在所述电介质覆盖层上沉积第二绝缘层; 蚀刻所述第二绝缘层的一部分以形成通孔开口，其中所述通孔开口暴露所述互连特征的一部分; 轰击互连特征的部分以在互连特征的一部分中定义测量特征; 蚀刻通孔测量特征，用于形成邻近互连特征和电介质覆盖层的底切区域; 沉积贵金属层，所述贵金属层填充通孔测量特征的底切区域以形成金属盖; 以及在所述金属盖上沉积金属层。

    IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA
    75.
    发明申请
    IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA 有权
    通过硅片的在线深度测量

    公开(公告)号：US20100210043A1

    公开(公告)日：2010-08-19

    申请号：US12371724

    申请日：2009-02-16

    申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

    IPC分类号： H01L21/66 ,  G06F19/00

    CPC分类号： H01L22/34 ,  H01L2924/3011

    摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

    摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

    ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD
    79.
    发明申请
    ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD 有权
    电可编程保险丝和制造方法

    公开(公告)号：US20100038747A1

    公开(公告)日：2010-02-18

    申请号：US12192387

    申请日：2008-08-15

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Joseph M. Lukaitis ,  Ping-Chuan Wang

    IPC分类号： H01L21/768 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

    摘要翻译： 电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。 阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近 阴极和熔断体连接处的连接处。

    Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems
    80.
    发明授权
    Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems 失效
    微机电系统的准确高效的质量和可靠性评估装置

    公开(公告)号：US07602265B2

    公开(公告)日：2009-10-13

    申请号：US11163485

    申请日：2005-10-20

    申请人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

    发明人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009

    摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

    摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。