公开(公告)号：US20200303280A1

公开(公告)日：2020-09-24

申请号：US16823895

申请日：2020-03-19

申请人： BRIDGE SEMICONDUCTOR CORP.

发明人： Charles W. C. LIN

IPC分类号： H01L23/367 ,  H01L23/373 ,  C25D7/12

摘要： An integrally formed metal layer is plated on spacers and a top surface of the heat spreader and a bottom surface of a heat generating component to establish a metallic interfacial structure that connects the heat generating component to the heat spreader. Accordingly, the heat can be conducted from the heat generating component to the heat spreader primarily through the metallic interfacial structure and the spacers.

公开(公告)号：US10781527B2

公开(公告)日：2020-09-22

申请号：US15707805

申请日：2017-09-18

申请人： Lam Research Corporation

发明人： Stephen J. Banik, II ,  Aaron Berke ,  Bryan L. Buckalew ,  Robert Rash

IPC分类号： C25B9/08 ,  C25B15/08 ,  C25B1/10 ,  C25B9/18 ,  C25D5/08 ,  C25D17/00 ,  C25D7/12 ,  C25D21/12 ,  H01L23/00 ,  H01L21/768 ,  H01L21/288

摘要： Various embodiments herein relate to methods and apparatus for electroplating material onto a semiconductor substrate. The apparatus includes an ionically resistive element that separates the plating chamber into a cross flow manifold (above the ionically resistive element) and an ionically resistive element manifold (below the ionically resistive element). Electrolyte is delivered to the cross flow manifold, where it shears over the surface of the substrate, and to the ionically resistive element manifold, where it passes through through-holes in the ionically resistive element to impinge upon the substrate as it enters the cross flow manifold. In certain embodiments, the flow of electrolyte into the cross flow manifold (e.g., through a side inlet) and the flow of electrolyte into the ionically resistive element manifold are actively controlled, e.g., using a three-way valve. In these or other cases, the ionically resistive element may include electrolyte jets.

公开(公告)号：US20200283924A1

公开(公告)日：2020-09-10

申请号：US16759994

申请日：2018-11-27

申请人： Linxens Holding

发明人： Hugues NSALAMBI ,  Florian VENON ,  Jérome SANSON ,  Guillaume CARDOSO

IPC分类号： C25D5/12 ,  C25D3/56 ,  C25D7/12 ,  G06K19/077 ,  H05K3/24 ,  H05K1/02

摘要： An electrical circuit, for example a printed circuit, for producing a module for integration into a card such as a chip card. This module includes electrical contact or connector which includes lands for the connection and communication of the chip with a read/write system. To give them a white color, or a color close to white, these electrical contact lands are at least partially covered with a layer of a rhodium alloy. The invention also relates to a method for manufacturing such an electrical circuit.

公开(公告)号：US10755900B2

公开(公告)日：2020-08-25

申请号：US15965794

申请日：2018-04-27

申请人： Applied Materials, Inc.

发明人： Toan Tran ,  Laksheswar Kalita ,  Tae Won Kim ,  Dmitry Lubomirsky ,  Xiaowei Wu ,  Xiao-Ming He ,  Cheng-Hsuan Chou ,  Jennifer Y. Sun

IPC分类号： C23C16/40 ,  H01J37/32 ,  C23C16/02 ,  C23C28/04 ,  C23C16/455 ,  C23C16/04 ,  C23C16/44 ,  C23C24/04 ,  C23C18/36 ,  C25D7/12

摘要： A method of applying a multi-layer plasma resistant coating on an article comprises performing plating or ALD to form a conformal first plasma resistant layer on an article, wherein the conformal first plasma resistant layer is formed on a surface of the article and on walls of high aspect ratio features in the article. The conformal first plasma resistant coating has a porosity of approximately 0% and a thickness of approximately 200 nm to approximately 1 micron. One of electron beam ion assisted deposition (EB-IAD), plasma enhanced chemical vapor deposition (PECVD), aerosol deposition or plasma spraying is then performed to form a second plasma resistant layer that covers the conformal first plasma resistant layer at a region of the surface but not at the walls of the high aspect ratio features.

公开(公告)号：US20200266165A1

公开(公告)日：2020-08-20

申请号：US16866709

申请日：2020-05-05

申请人： Rohm and Haas Electronic Materials LLC

发明人： Ravi POKHREL ,  Michael K. Gallagher

IPC分类号： H01L23/00 ,  C25D5/10 ,  C25D7/12 ,  C25D5/02

摘要： The copper pillars have improved integrity such that they can readily withstand the harsh reflow conditions of post solder bump application without readily failing. The method of making the copper pillars having the improved integrity involves a two-step electroplating process of varying current densities.

公开(公告)号：US10741513B2

公开(公告)日：2020-08-11

申请号：US16226173

申请日：2018-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Fu Shih ,  Chun-Yen Lo ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chien-Ming Huang ,  Yuan-Fu Liu ,  Yung-Chiuan Cheng ,  Wei-Chih Huang ,  Chen-Hsun Liu ,  Chien-Pin Chan ,  Yu-Nu Hsu ,  Chi-Hung Lin ,  Te-Hsun Pang ,  Chin-Yu Ku

IPC分类号： H01L23/00 ,  C25D5/50 ,  C25D17/12 ,  C25D5/12 ,  C25D17/00 ,  C25D7/12 ,  C25D21/10 ,  H01L23/31 ,  C25D3/12 ,  C25D3/38 ,  C25D3/60

摘要： External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

公开(公告)号：US10727169B2

公开(公告)日：2020-07-28

申请号：US16364517

申请日：2019-03-26

申请人： Rohm Co., Ltd.

发明人： Koshun Saito

IPC分类号： H01L23/49 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  C23F17/00 ,  C25D7/12 ,  H01L21/48

摘要： A semiconductor device includes a semiconductor element, a plurality of leads electrically connected to the semiconductor element and one of which supports the semiconductor element, a sealing resin covering the semiconductor element and a portion of each leads, and first and second plating layers exposed from the sealing resin. The sealing resin includes a resin side surface facing in a first direction perpendicular to the thickness direction. At least one of the leads has a lead end surface connected to its back surface and flush with the resin side surface. The first plating layer covers the back surface of the lead. The second plating layer covers the lead end surface and projects in the first direction relative to the resin side surface. An edge of the second plating layer overlaps with the first plating layer as viewed in the first direction.

公开(公告)号：US20200234958A1

公开(公告)日：2020-07-23

申请号：US16552314

申请日：2019-08-27

申请人： Ontos Equipment Systems

发明人： Eric Frank Schulte

IPC分类号： H01L21/288 ,  H01L21/02 ,  C25D7/12 ,  C25D5/34 ,  C25D5/02 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/027 ,  C25D17/00

摘要： Methods and systems for using the downstream active residuals of a reducing-chemistry atmospheric plasma to provide multiple advantages to pre-plating surface preparation with a simple apparatus. As the downstream active species of the atmospheric plasma impinge the substrate surface, three important surface preparation processes can be performed simultaneously: 1. Organic residue is removed from the surface of the plating base. 2. Oxidation is removed from the surface of the plating base. 3. All surfaces on the substrate are highly activated by the downstream active residuals thus creating a highly wettable surface for subsequent plating operations.

公开(公告)号：US20200211952A1

公开(公告)日：2020-07-02

申请号：US16814215

申请日：2020-03-10

申请人： Intel Corporation

发明人： Rahul N. Manepalli ,  Kousik Ganesan ,  Marcel Arlan Wall ,  Srinivas Pietambaram

IPC分类号： H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/10 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

摘要： According to various embodiments of the present disclosure, a substrate for an integrated circuit includes a dielectric layer. The substrate further includes a conductive layer extending in an x or y direction. The conductive layer is at least partially embedded within the dielectric layer. The conductive layer includes a via having a first end and an opposite second end. The via has a first height in a z-direction and a constant cross-sectional shape between the first end and the second end. A trace is adjacent to the via and has a second height in the z-direction that is different than the first height.

公开(公告)号：US20200209099A1

公开(公告)日：2020-07-02

申请号：US16711983

申请日：2019-12-12

申请人： EBARA CORPORATION

发明人： Kiyoshi Suzuki ,  Jumpei Fujikata

IPC分类号： G01M3/32 ,  C25D7/12 ,  C25D21/12 ,  C25D17/00 ,  C25D17/06

摘要： A leak check method includes: performing a first inspection of measuring a pressure in an internal space formed by a seal of the substrate holder, while evacuating the internal space, and detecting that the pressure reaches a first pressure threshold value within a predetermined first inspection time; performing a second inspection of closing the internal space that has been evacuated, measuring the pressure in the closed internal space, and detecting that the pressure in the closed internal space does not exceed a second pressure threshold value within a predetermined second inspection time; and performing a third inspection of measuring a pressure difference between the pressure in the closed internal space and a vacuum pressure in a master container, and detecting that an amount of increase in the pressure difference within a predetermined third inspection time is kept equal to or below a pressure difference threshold value.