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71.发明授权Self-reset transient-to-digital convertor and electronic product utilizing the same 有权自复位瞬态到数字转换器和使用它的电子产品公开(公告)号：US09001478B2
公开(公告)日：2015-04-07
申请号：US13329033
申请日：2011-12-16
CPC分类号： H03M1/361 , G01R19/0053
摘要： A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.
摘要翻译： 公开了一种包括至少一个瞬态检测电路的自复位瞬态 - 数字转换器。 耦合在第一电力线和第二电力线之间的瞬态检测电路包括至少一个压降单元，电流放大器单元和时间控制单元。 当ESD事件发生时，电压降单元被传导通过ESD电流。 耦合在电压降单元和第一电力线之间的电流放大器单元由ESD电流进行，以设定第一节点的电平。 耦合在第一节点和第二电力线之间的时间控制单元配置成逐渐将ESD电流消耗掉。 其中，每个瞬态检测电路根据第一节点的电平产生数字码。
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公开(公告)号：US08994570B1
公开(公告)日：2015-03-31
申请号：US14037962
申请日：2013-09-26
发明人： Hashem Zare-Hoseini
摘要： An analog-to-digital converter employs one or more reference ladders for generating reference voltages with which to compare the analog signal for quantization. Selected impedances of the reference ladder can be dynamically decoupled from the input signal in dependence on the value of the output signal in order to reduce headroom in the reference ladders, thus making possible accurate quantization in low-voltage applications.
摘要翻译： 模数转换器采用一个或多个参考电梯来产生用于比较模拟信号进行量化的参考电压。 参考梯形图的选定阻抗可以根据输出信号的值从输入信号中动态解耦，以减少参考梯形图中的余量，从而使得低电压应用中的精确量化成为可能。
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公开(公告)号：US08988265B2
公开(公告)日：2015-03-24
申请号：US13941598
申请日：2013-07-15
申请人： MediaTek Inc.
发明人： Yun-Shiang Shu
摘要： A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.
摘要翻译： 提供比较电路并包括第一和第二比较器和第一时间 - 数字比较器。 具有第一偏移电压的第一比较器接收输入信号并产生第一比较信号和第一反比较信号。 第二比较器接收输入信号并产生第二比较信号和第二反比较信号。 第一偏移电压大于第二偏移电压。 第一时间数字比较器接收第一比较信号和第二反比较信号，并根据第一比较信号和第二反比较信号产生第一和第二确定信号。 第一和第二确定信号指示输入信号的电压是否大于第一中间电压。 第一中间电压等于第一偏移电压和第二偏移电压之和的一半。
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公开(公告)号：US20150015229A1
公开(公告)日：2015-01-15
申请号：US14159917
申请日：2014-01-21
发明人： Chen Kong Teh
摘要： A feedback loop, which feedbacks information of an output voltage or a load current, is provided. The feedback loop has a first mode, which digitalizes and feedbacks the information of the current voltage or the load current, and a second mode, which feedbacks the information as an analog value.
摘要翻译： 提供反馈输出电压或负载电流信息的反馈回路。 反馈回路具有对当前电压或负载电流的信息进行数字化和反馈的第一模式，以及将信息反馈为模拟值的第二模式。
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公开(公告)号：US08928508B2
公开(公告)日：2015-01-06
申请号：US13526147
申请日：2012-06-18
CPC分类号： H03M1/1009 , H03M1/1004 , H03M1/365
摘要： An analog-to-digital converter (ADC) including a plurality of comparators connected to the ADC. The ADC further includes a first pair of terminals and a second pair of terminals connected to each of the plurality of comparators. The ADC further includes a first pair of switches coupled to each of the first pair of terminals and a second pair of switches coupled to each of the second pair of terminals, where the first and second pair of switches are configured to alternate a corresponding comparator between normal operation and a calibration configuration. Comparators other than the corresponding comparator are configured for normal operation if the corresponding comparator is configured to be calibrated.
摘要翻译： 包括连接到ADC的多个比较器的模数转换器（ADC）。 ADC还包括连接到多个比较器中的每一个的第一对端子和第二对端子。 ADC还包括耦合到第一对端子中的每一个的第一对开关和耦合到第二对端子中的每一个的第二对开关，其中第一和第二对开关被配置为在 正常操作和校准配置。 如果对应的比较器被配置为校准，则比较器对应的比较器被配置为正常运行。
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公开(公告)号：US08890739B2
公开(公告)日：2014-11-18
申请号：US13706035
申请日：2012-12-05
发明人： Donald E. Lewis , Ryan James Kier , Rex K. Hales , Yusuf Haque
CPC分类号： H03M1/1061 , H03M1/1245 , H03M1/164
摘要： A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
摘要翻译： 时间交织模数转换器（ADC）包括多个ADC; 定时发生器，用于为每个ADC产生时钟信号，使得所述时钟信号的边沿触发ADC的输入信号的采样; 以及定时调整电路，用于在由ADC接收时钟信号之前接收和调整时钟信号，使得所述输入信号的采样在时间上间隔并以所需采样速率的1 / N倍的速率发生; 以及用于调整多个ADC的带宽的电路。
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公开(公告)号：US08878712B2
公开(公告)日：2014-11-04
申请号：US13829257
申请日：2013-03-14
CPC分类号： H03M1/0673 , H03M1/145 , H03M1/365
摘要： A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.
摘要翻译： 闪存ADC电路可以包括提供参考信号的参考梯形图和多个比较器，每个比较器基于一对输入信号与一对参考信号的比较来提供输出。 至少一对比较器可以在每个比较器处以不同的参考信号取向接收相同的一对参考信号。 闪存ADC可以包括用于在一对比较器之间交换一对参考信号的开关网络。
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公开(公告)号：US08723713B2
公开(公告)日：2014-05-13
申请号：US13717410
申请日：2012-12-17
申请人： Junya Matsuno , Tetsuro Itakura
发明人： Junya Matsuno , Tetsuro Itakura
IPC分类号： H03M1/36
摘要： There is provided a signal interpolation device, including: a first amplifier to generate a first signal representing a difference between an input signal and a first reference voltage; a second amplifier to generate a second signal representing a difference between the input signal and a second reference voltage; a first output amplifier to amplify the first signal to generate a first output signal; a second output amplifier to amplify the second signal to generate a second output signal; a third output amplifier to amplify a sum of a first interpolation signal and the first signal to generate a third output signal, the first interpolation signal representing a voltage generated by dividing a difference between the first reference voltage and the second reference voltage by “2^n”; and a fourth output amplifier to amplify a difference between the second signal and the first interpolation signal to generate a fourth output signal.
摘要翻译： 提供了一种信号插值装置，包括：第一放大器，用于产生表示输入信号和第一参考电压之间的差的第一信号; 第二放大器，用于产生表示所述输入信号和第二参考电压之间的差的第二信号; 第一输出放大器，用于放大第一信号以产生第一输出信号; 第二输出放大器，用于放大第二信号以产生第二输出信号; 第三输出放大器，用于放大第一内插信号和第一信号的和以产生第三输出信号，第一内插信号表示通过将第一参考电压和第二参考电压之差除以“2 ^ n“; 以及第四输出放大器，用于放大第二信号和第一内插信号之间的差以产生第四输出信号。
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79.发明申请AD CONVERTING CIRCUIT, PHOTOELECTRIC CONVERTING APPARATUS, IMAGE PICKUP SYSTEM, AND DRIVING METHOD FOR AD CONVERTING CIRCUIT 审中-公开AD转换电路，光电转换设备，图像拾取系统和AD转换电路的驱动方法公开(公告)号：US20140078362A1
公开(公告)日：2014-03-20
申请号：US14082809
申请日：2013-11-18
发明人： Daisuke Yoshida
摘要： An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.
摘要翻译： 用于通过第二级AD转换获得i位数字码和通过第二级AD转换的j位数字码的装置包括：比较单元，用于比较第一级AD转换中的参考信号和模拟信号; 以及放大单元，用于输出通过放大模拟信号和对应于i位数字码的模拟信号之间的差而获得的放大残差信号。 比较单元将放大的残差信号与第二级AD转换中的参考信号进行比较。
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公开(公告)号：US20120206281A1
公开(公告)日：2012-08-16
申请号：US13025855
申请日：2011-02-11
申请人： Rizwan BASHIRULLAH , Jikai CHEN
发明人： Rizwan BASHIRULLAH , Jikai CHEN
CPC分类号： H03M1/1061 , H03M1/1004 , H03M1/365
摘要： Calibration of an analog-to-digital converter (ADC) is accomplished via a reference comparator, a first and second multiplexer (MUX), and a finite state machine (FSM). By sampling an analog input with the reference comparator and comparing the results with those of the ADC using the FSM, all the comparators in the ADC can be calibrated without interrupting the ADC's normal operation. The first MUX provides a same reference voltage to the reference comparator as a comparator selected for the calibration, and the second MUX provides the FSM with the output of the selected comparator. The FSM then performs a comparison of the reference comparator and the selected comparator, extracts the polarity of the mismatch, and updates the contents of a memory with the extracted polarity. An offset control in the selected comparator receives a signal corresponding to the extracted polarity stored in the memory and injects offset current into the comparator.
摘要翻译： 模数转换器（ADC）的校准通过参考比较器，第一和第二多路复用器（MUX）和有限状态机（FSM）来实现。 通过使用参考比较器对模拟输入进行采样，并使用FSM将结果与ADC的结果进行比较，ADC中的所有比较器都可以在不中断ADC正常运行的情况下进行校准。 第一MUX为参考比较器提供相同的参考电压作为选择用于校准的比较器，而第二MUX为FSM提供所选比较器的输出。 然后，FSM执行参考比较器和所选比较器的比较，提取失配的极性，并以提取的极性更新存储器的内容。 所选择的比较器中的偏移控制器接收对应于存储在存储器中的提取的极性的信号，并将偏移电流注入比较器。
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