公开(公告)号：US20190341460A1

公开(公告)日：2019-11-07

申请号：US16511562

申请日：2019-07-15

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Yasutaka NAKAZAWA ,  Masashi OOTA

IPC分类号： H01L29/24 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/267 ,  H01L29/12 ,  H01L29/43

摘要： The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed using a composite oxide semiconductor in which a first region and a second region are mixed. The first region includes a plurality of first clusters containing one or more of indium, zinc, and oxygen as a main component. The second region includes a plurality of second clusters containing one or more of indium, an element M (M represents Al, Ga, Y, or Sn), zinc, and oxygen. The first region includes a portion in which the plurality of first clusters are connected to each other. The second region includes a portion in which the plurality of second clusters are connected to each other.

公开(公告)号：US10468473B2

公开(公告)日：2019-11-05

申请号：US15389990

申请日：2016-12-23

申请人： LG Display Co., Ltd.

发明人： Jiyeon Kang ,  Changeun Kim ,  Jeongeun Baek ,  Sungjin Kim

IPC分类号： H01L27/32 ,  H01L51/05 ,  H01L29/267 ,  G02F1/1368 ,  H01L51/00 ,  H01L51/52 ,  H01L29/786

摘要： Carbon allotropes, a thin-film transistor array substrate comprising the same, and a display device comprising the same are disclosed. The thin-film transistor array substrate comprising a substrate, a gate electrode on the substrate, a gate insulating film on the gate electrode, an active layer positioned on the gate insulating film and comprising a semiconductor material and a plurality of carbon allotropes, and a source electrode and a drain electrode that make contact with the active layer.

公开(公告)号：US10461179B2

公开(公告)日：2019-10-29

申请号：US15905978

申请日：2018-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jean-Pierre Colinge ,  Carlos H Diaz ,  Yee-Chia Yeo

IPC分类号： H01L21/461 ,  H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L27/088 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L21/477 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/426 ,  H01L21/441 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

摘要： Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US10461074B2

公开(公告)日：2019-10-29

申请号：US16022263

申请日：2018-06-28

申请人： Infineon Technologies Austria AG

发明人： Wolfgang Werner

IPC分类号： H01L29/66 ,  H01L27/06 ,  H01L29/872 ,  H01L29/78 ,  H01L29/267 ,  H01L29/808 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/861 ,  H01L29/10 ,  H01L29/739

摘要： According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of monocrystalline SiC, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the monocrystalline SiC directly adjoining the drift region and the metallization, and an anode region of a semiconductor material having a lower band-gap than the monocrystalline SiC. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

公开(公告)号：US10446705B2

公开(公告)日：2019-10-15

申请号：US15507621

申请日：2015-07-30

申请人： Konica Minolta Laboratory U.S.A., Inc.

发明人： Jun Amano

IPC分类号： H01L31/0352 ,  H01L31/18 ,  H01L31/0224 ,  H01L29/24 ,  H01L21/02 ,  H01L29/267 ,  H01L29/12 ,  H01L29/861 ,  B82Y10/00 ,  B82Y20/00 ,  B82Y30/00 ,  H01L31/0304 ,  H01L31/032 ,  H01L33/06 ,  H01L33/26 ,  H01L29/20

摘要： A quantum well device includes a first layer of a first two-dimensional material, a second layer of a second two-dimensional material, and a third layer of a third two-dimensional material disposed between the first layer and second layer. The first layer, the second layer, and the third layer are adhered predominantly by van der Waals force.

公开(公告)号：US10446668B2

公开(公告)日：2019-10-15

申请号：US14934417

申请日：2015-11-06

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki

IPC分类号： H01L29/66 ,  H01L29/267 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/118 ,  H01L27/12 ,  H01L21/3105 ,  H01L21/324 ,  H01L29/10 ,  H01L29/49

摘要： To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first to a third oxide semiconductor layers are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first and the third oxide semiconductor layers are each an amorphous semiconductor film. The second oxide semiconductor layer is a crystalline semiconductor film.

公开(公告)号：US20190288122A1

公开(公告)日：2019-09-19

申请号：US16501731

申请日：2019-05-28

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Archana Venugopal ,  Luigi Colombo ,  Arup Polley

IPC分类号： H01L29/786 ,  H01L29/16 ,  H01L21/02 ,  H01L29/20 ,  H01L29/267 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49

摘要： A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

公开(公告)号：US20190287865A1

公开(公告)日：2019-09-19

申请号：US16421009

申请日：2019-05-23

申请人： Institute of Microelectronics, Chinese Academy of Sciences

发明人： Huilong Zhu ,  Zhengyong Zhu

IPC分类号： H01L21/8238 ,  H01L29/267 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165 ,  H01L21/308 ,  H01L21/822 ,  H01L27/092 ,  H01L29/205 ,  H01L21/225 ,  H01L21/324 ,  H01L29/10 ,  H01L29/15 ,  H01L29/778 ,  H01L29/45 ,  H01L21/3065 ,  H01L29/04

摘要： There are provided an Integrated Circuit (IC) unit, a method of manufacturing the same, and an electronic device including the IC unit. According to an embodiment, the IC unit includes a first source/drain layer, a channel layer and a second source/drain layer for a first device and a first source/drain layer, a channel layer and a second source/drain layer for a second device stacked in sequence on a substrate. In the first device, the channel layer includes a first portion and a second portion separated from each other. The first source/rain layer and the second source/drain layer each extend integrally to overlap both the first portion and the second portion of the channel layer. The IC unit further includes a first gate stack surrounding a periphery of the first portion and also a periphery of the second portion of the channel layer of the first device, and a second gate stack surrounding a periphery of the channel layer of the second device.

公开(公告)号：US20190287789A1

公开(公告)日：2019-09-19

申请号：US16431646

申请日：2019-06-04

申请人： Intel Corporation

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/267 ,  H01L29/20 ,  H01L29/16 ,  H01L29/06 ,  H01L29/04 ,  H01L27/06 ,  H01L21/8252

摘要： III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

公开(公告)号：US20190273159A1

公开(公告)日：2019-09-05

申请号：US16416725

申请日：2019-05-20

申请人： Samsung Electronics Co., Ltd.

发明人： Jae-hoon LEE ,  Gi-gwan Park ,  Tae-Young Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/08 ,  H01L29/22 ,  H01L29/267 ,  H01L29/15 ,  H01L29/16

摘要： A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.