公开(公告)号：US10461179B2

公开(公告)日：2019-10-29

申请号：US15905978

申请日：2018-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jean-Pierre Colinge ,  Carlos H Diaz ,  Yee-Chia Yeo

IPC分类号： H01L21/461 ,  H01L29/66 ,  H01L29/267 ,  H01L29/78 ,  H01L27/088 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L21/477 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/426 ,  H01L21/441 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24 ,  H01L29/423 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

摘要： Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US09899269B2

公开(公告)日：2018-02-20

申请号：US14983816

申请日：2015-12-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Carlos H Diaz ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L27/092

CPC分类号： H01L21/823821 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/7831

摘要： A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.

公开(公告)号：US20190140075A1

公开(公告)日：2019-05-09

申请号：US16222131

申请日：2018-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H Diaz

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L29/66545 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

公开(公告)号：US10157799B2

公开(公告)日：2018-12-18

申请号：US15880584

申请日：2018-01-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Carlos H Diaz ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L21/78 ,  H01L21/8234

摘要： A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.

公开(公告)号：US09882032B2

公开(公告)日：2018-01-30

申请号：US15401867

申请日：2017-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Carlos H Diaz

IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02 ,  H01L21/225 ,  H01L21/28

CPC分类号： H01L29/66818 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2255 ,  H01L21/28167 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7849 ,  H01L29/785

摘要： A method includes forming isolation features on a substrate, thereby defining an active region on the semiconductor substrate; recessing the active region to form a fin trench; forming a fin feature on the fin trench by growing a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer; performing a first recessing process; forming a dummy gate stack over the fin feature and the isolation feature; performing a thermal oxidation process to selectively oxidize the first semiconductor layer to form a semiconductor oxide feature on sidewalls of the first semiconductor layer; performing a second recessing process such that a portion of the isolation feature is recessed to below the second semiconductor layer, resulting in a dented void overlying the semiconductor oxide feature and underlying the second semiconductor layer; and forming a gate stack including a gate dielectric layer extending to the dented void.

公开(公告)号：US10727314B2

公开(公告)日：2020-07-28

申请号：US16222131

申请日：2018-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H Diaz

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

公开(公告)号：US10157999B2

公开(公告)日：2018-12-18

申请号：US15819952

申请日：2017-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H Diaz

IPC分类号： H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/24 ,  H01L29/267 ,  H01L29/06

摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

公开(公告)号：US09929257B2

公开(公告)日：2018-03-27

申请号：US15404712

申请日：2017-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jean-Pierre Colinge ,  Carlos H Diaz ,  Yee-Chia Yeo

IPC分类号： H01L29/66 ,  H01L21/441 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8256 ,  H01L29/06 ,  H01L29/08 ,  H01L29/24 ,  H01L21/762 ,  H01L21/426 ,  H01L21/461 ,  H01L29/78 ,  H01L21/477

CPC分类号： H01L29/66969 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02667 ,  H01L21/426 ,  H01L21/441 ,  H01L21/461 ,  H01L21/477 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823885 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/127 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

摘要： Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

公开(公告)号：US20170117391A1

公开(公告)日：2017-04-27

申请号：US15401867

申请日：2017-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Zhiqiang Wu ,  Carlos H Diaz

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/225 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/66818 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2255 ,  H01L21/28167 ,  H01L29/1054 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7849 ,  H01L29/785

摘要： A method includes forming isolation features on a substrate, thereby defining an active region on the semiconductor substrate; recessing the active region to form a fin trench; forming a fin feature on the fin trench by growing a first semiconductor layer on the substrate and a second semiconductor layer on the first semiconductor layer; performing a first recessing process; forming a dummy gate stack over the fin feature and the isolation feature; performing a thermal oxidation process to selectively oxidize the first semiconductor layer to form a semiconductor oxide feature on sidewalls of the first semiconductor layer; performing a second recessing process such that a portion of the isolation feature is recessed to below the second semiconductor layer, resulting in a dented void overlying the semiconductor oxide feature and underlying the second semiconductor layer; and forming a gate stack including a gate dielectric layer extending to the dented void.