公开(公告)号：US09793919B1

公开(公告)日：2017-10-17

申请号：US15373105

申请日：2016-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Greggory D. Donley ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard

IPC: H03M7/00 ,  H03M7/30 ,  H04B1/40 ,  H04L27/26 ,  H04L1/06 ,  H04L1/00 ,  H04L25/02

CPC classification number: H03M7/30 ,  G06K9/6202 ,  H03M7/3084 ,  H03M7/42 ,  H04B1/40 ,  H04L1/0003 ,  H04L1/0618 ,  H04L25/0266 ,  H04L27/2647 ,  H04L67/14

Abstract: Systems, apparatuses, and methods for compression of frequent data values across narrow links are disclosed. In one embodiment, a system includes a processor, a link interface unit, and a communication link. The link interface unit is configured to receive a data stream for transmission over the communication link, wherein the data stream is generated by the processor. The link interface unit determines if blocks of data of a first size from the data stream match one or more first data patterns and the link interface unit determines if blocks of data of a second size from the data stream match one or more second data patterns. The link interface unit sends, over the communication link, only blocks of data which do not match the first or second data patterns.

公开(公告)号：US09785345B2

公开(公告)日：2017-10-10

申请号：US15379956

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Yunpeng Zhu ,  Xianshuai Shi ,  Yan Liu

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0604 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/401 ,  G06F2212/657 ,  Y02D10/13

Abstract: A system has a plurality of functional modules including a first functional module and one or more other functional modules. The first functional module includes an embedded memory element and is configurable in a plurality of modes including a first mode and a second mode. When the first functional module is in the first mode, access to the embedded memory element is limited to the first functional module. At least one of the one or more other functional modules is provided with access to the embedded memory element based at least in part on the first functional module being in the second mode.

公开(公告)号：US09785218B2

公开(公告)日：2017-10-10

申请号：US14846058

申请日：2015-09-04

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Adam N. C. Clark ,  Ashish Jain ,  Sridhar V. Gada

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

公开(公告)号：US20170277639A1

公开(公告)日：2017-09-28

申请号：US15361335

申请日：2016-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amro Awad ,  Sergey Blagodurov ,  Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/65 ,  G06F2212/683

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB). During operation, the computing device updates an entry in the TLB based on a virtual address to physical address translation and metadata from a page table entry that were acquired during a page table walk. The computing device then computes, based on a lease length expression, a lease length for the entry in the TLB. Next, the computing device sets, for the entry in the TLB, a lease value to the lease length, wherein the lease value represents a time until a lease for the entry in the TLB expires, wherein the entry in the TLB is invalid when the associated lease has expired. The computing device then uses the lease value to control operations that are allowed to be performed using information from the entry in the TLB.

公开(公告)号：US20170277441A1

公开(公告)日：2017-09-28

申请号：US15331270

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Gupta ,  David A. Roberts ,  Mitesh R. Meswani ,  Vilas Sridharan ,  Steven Raasch ,  Daniel I. Lowell

IPC: G06F3/06

CPC classification number: G06F12/02

Abstract: Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.

公开(公告)号：US09767043B2

公开(公告)日：2017-09-19

申请号：US14229420

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/126 ,  G06F3/06 ,  G06F12/00 ,  G06F12/0871 ,  G06F12/0808 ,  G06F12/02 ,  G06F12/12 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/126 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0628 ,  G06F3/0653 ,  G06F3/0673 ,  G06F3/0674 ,  G06F3/0676 ,  G06F12/00 ,  G06F12/02 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0871 ,  G06F12/12 ,  G06F12/121

Abstract: A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping.

公开(公告)号：US09760145B2

公开(公告)日：2017-09-12

申请号：US14716314

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Madhu S. S. Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172

Abstract: A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector. The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.

公开(公告)号：US09740611B2

公开(公告)日：2017-08-22

申请号：US14526856

申请日：2014-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Yair Shachar ,  Einav Raizman-Kedar ,  Evgeny Pinchuk

IPC: G06T1/60 ,  G06F12/08 ,  G06F12/1081 ,  G06F9/45 ,  G06F11/34

CPC classification number: G06F12/08 ,  G06F8/41 ,  G06F11/34 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/601 ,  G06F2212/6028 ,  G06T1/60

Abstract: A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the memory usage of an application are provided to a page manager. At least one runtime memory usage pattern of the application is sent to the page manager. Data is swapped into and out of a memory by analyzing the hints and the at least one runtime memory usage pattern.

公开(公告)号：US20170223370A1

公开(公告)日：2017-08-03

申请号：US15491887

申请日：2017-04-19

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Haibin Li ,  Zhen Chen ,  Lei Zhang ,  Ji Zhou ,  Zhong Cai

IPC: H04N19/436 ,  H04N19/15

CPC classification number: H04N19/436 ,  H04N19/15 ,  H04N19/176 ,  H04N19/182 ,  H04N19/184 ,  H04N19/423

Abstract: A system and method for providing video compression that includes encoding using an encoding engine a YUV stream wherein Y, U and V color values are encoded in parallel and patching together the Y, U and V color streams to form a compressed YUV output stream. The encoding engine further includes encoding each color value of the YUV stream in parallel using parallel encoding engines and a control engine for controlling operation all of the encoding engines in parallel. The YUV stream has an average bits per pixel value that varies from a first value to a second value that is double the first value. The encoding engine includes encoding the YUV stream in generally the same amount of time regardless of the average bits per pixel value.

公开(公告)号：US09720486B2

公开(公告)日：2017-08-01

申请号：US14865928

申请日：2015-09-25

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Angel E. Socarras ,  Fei Guo

IPC: G06F1/32 ,  G06F1/06

CPC classification number: G06F1/324 ,  G06F1/06 ,  G06F1/10 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/152

Abstract: A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.