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81.发明申请LEAKAGE COMPENSATION CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS 有权用于动态随机存取存储器（DRAM）电池的泄漏补偿电路公开(公告)号：US20100073994A1
公开(公告)日：2010-03-25
申请号：US12236302
申请日：2008-09-23
Applicant: DiaaEldin S. Khalil , Arijit Rayehowdhury , Muhammad M. Khellah , Ali Keshavarzi
Inventor： DiaaEldin S. Khalil , Arijit Rayehowdhury , Muhammad M. Khellah , Ali Keshavarzi
CPC classification number: G11C8/14 , G11C11/404 , G11C11/4085 , G11C11/4094
Abstract: A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.
Abstract translation: 一种包括泄漏补偿电路的动态随机存取存储器（DRAM）单元。 泄漏补偿电路允许来自源的补偿电流流向DRAM单元的存储单元存储节点，以补偿来自DRAM单元的存储单元存储节点的泄漏电流，以改善保持时间。
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82.发明授权Floating-body dynamic random access memory and method of fabrication in tri-gate technology 有权浮动动态随机存取存储器及三栅极技术制造方法公开(公告)号：US07514746B2
公开(公告)日：2009-04-07
申请号：US11429490
申请日：2006-05-04
Applicant: Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Brian Doyle , Suman Datta , Vivek K. De
Inventor： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Brian Doyle , Suman Datta , Vivek K. De
IPC: H01L27/01 , H01L27/12 , H01L31/0392
CPC classification number: H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
Abstract translation: 浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。 可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。 栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。 栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。
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公开(公告)号：US07501316B2
公开(公告)日：2009-03-10
申请号：US11268098
申请日：2005-11-07
Applicant: Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
Inventor： Ali Keshavarzi , Stephen H. Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC: H01L21/82
CPC classification number: G11C11/404 , G11C2211/4016 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L29/7841
Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
Abstract translation: 一些实施例提供了包括体区，源区和漏区的存储单元。 主体区域掺杂有第一类型的电荷载流子，源极区域设置在体区中并掺杂有第二类型的电荷载流子，并且漏极区域设置在体区中并掺杂有第二类型的载流子 类型。 主体区域和源极区域形成第一结，主体区域和漏极区域形成第二结，并且在第一接合点不偏向的情况下，从体区域到源极区域的第一结的导电率基本上 在第二接头不偏差的情况下，小于从体区到漏区的第二结的导电性。
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公开(公告)号：US20090003028A1
公开(公告)日：2009-01-01
申请号：US11824321
申请日：2007-06-29
Applicant: Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
Inventor： Ali Keshavarzi , Juanita Kurtin , Janice C. Lee , Vivek De , Tanay Karnik , Timothy L. Deeter
CPC classification number: G11C17/16 , B82Y10/00 , G11C13/025 , G11C17/165 , G11C2213/17 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.
Abstract translation: 在本发明的一个实施例中，用于一次可编程存储器的熔丝元件可以包括耦合到第一晶体管节点和第二晶体管节点的碳纳米管。 碳纳米管可以具有在以低电流水平编程存储器单元时可以改变的第一电阻。
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公开(公告)号：US07295474B2
公开(公告)日：2007-11-13
申请号：US11172742
申请日：2005-06-30
Applicant: Yibin Ye , Muhammad M. Khellah , Dinesh Somasekhar , Ali Keshavarzi , Fabrice Paillet , Vivek K. De
Inventor： Yibin Ye , Muhammad M. Khellah , Dinesh Somasekhar , Ali Keshavarzi , Fabrice Paillet , Vivek K. De
IPC: G11C11/34
CPC classification number: G11C11/405 , G11C7/062 , G11C7/067 , G11C7/12 , G11C11/4085 , G11C11/4091 , G11C11/4094
Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.
Abstract translation: 写入信息存储单元阵列中的单元，通过将耦合到单元的位线和阵列中的一组其他单元的信号置为第一电压。 通过在与第一电压的方向但不达到第一电压的方向上断言在字线上耦合到单元和阵列中的另一组单元的信号来读取单元。 还描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US07262107B2
公开(公告)日：2007-08-28
申请号：US11170504
申请日：2005-06-29
Applicant: Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
Inventor： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
IPC: H01L21/331
CPC classification number: H01L27/108 , H01L27/1085 , H01L28/40
Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
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公开(公告)号：US07236410B2
公开(公告)日：2007-06-26
申请号：US11169106
申请日：2005-06-27
Applicant: Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad M. Khellah , Vivek K. De
Inventor： Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad M. Khellah , Vivek K. De
CPC classification number: G11C17/18
Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
Abstract translation: 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号，电源电压以及多个轨道电压中的一个或多个，多个轨道电压中的每一个基本上等于电源电压的相应整数倍， 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管，多个晶体管中的每一个的栅极电压至少部分地由第二控制信号，电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。
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88.发明申请公开(公告)号：US20060267093A1
公开(公告)日：2006-11-30
申请号：US11429490
申请日：2006-05-04
Applicant: Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
Inventor： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC: H01L27/12
CPC classification number: H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
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公开(公告)号：US20060187706A1
公开(公告)日：2006-08-24
申请号：US11008666
申请日：2005-02-22
Applicant: Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
Inventor： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Vivek De
IPC: G11C11/34
CPC classification number: G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
Abstract translation: 动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。 控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。 增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。
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公开(公告)号：US07075821B2
公开(公告)日：2006-07-11
申请号：US10956407
申请日：2004-09-30
Applicant: Yibin Ye , Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Gerhard Schrom , Vivek K. De
Inventor： Yibin Ye , Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Gerhard Schrom , Vivek K. De
IPC: G11C7/00
CPC classification number: G11C11/404 , G11C2211/4016
Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.
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